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Commit a5073d60 authored by Yixian Liu's avatar Yixian Liu Committed by Jason Gunthorpe
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RDMA/hns: Add eq support of hip08 



This patch adds eq support for hip08. The eq table can
be multi-hop addressed.

Signed-off-by: default avatarYixian Liu <liuyixian@huawei.com>
Reviewed-by: default avatarLijun Ou <oulijun@huawei.com>
Reviewed-by: default avatarWei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@mellanox.com>
parent b16f8188

drivers/infiniband/hw/hns/hns_roce_cmd.h

+10 −0
Original line number Diff line number Diff line
@@ -88,6 +88,16 @@ enum { 
	HNS_ROCE_CMD_DESTROY_SRQC_BT0	= 0x38,

	HNS_ROCE_CMD_DESTROY_SRQC_BT1	= 0x39,

	HNS_ROCE_CMD_DESTROY_SRQC_BT2	= 0x3a,



	/* EQC commands */

	HNS_ROCE_CMD_CREATE_AEQC	= 0x80,

	HNS_ROCE_CMD_MODIFY_AEQC	= 0x81,

	HNS_ROCE_CMD_QUERY_AEQC		= 0x82,

	HNS_ROCE_CMD_DESTROY_AEQC	= 0x83,

	HNS_ROCE_CMD_CREATE_CEQC	= 0x90,

	HNS_ROCE_CMD_MODIFY_CEQC	= 0x91,

	HNS_ROCE_CMD_QUERY_CEQC		= 0x92,

	HNS_ROCE_CMD_DESTROY_CEQC	= 0x93,

};



enum {

drivers/infiniband/hw/hns/hns_roce_common.h

+11 −0
Original line number Diff line number Diff line
@@ -376,6 +376,12 @@ 
#define ROCEE_RX_CMQ_TAIL_REG			0x07024

#define ROCEE_RX_CMQ_HEAD_REG			0x07028



#define ROCEE_VF_MB_CFG0_REG			0x40

#define ROCEE_VF_MB_STATUS_REG			0x58



#define ROCEE_VF_EQ_DB_CFG0_REG			0x238

#define ROCEE_VF_EQ_DB_CFG1_REG			0x23C



#define ROCEE_VF_SMAC_CFG0_REG			0x12000

#define ROCEE_VF_SMAC_CFG1_REG			0x12004
@@ -385,4 +391,9 @@ 
#define ROCEE_VF_SGID_CFG3_REG			0x1000c

#define ROCEE_VF_SGID_CFG4_REG			0x10010



#define ROCEE_VF_ABN_INT_CFG_REG		0x13000

#define ROCEE_VF_ABN_INT_ST_REG			0x13004

#define ROCEE_VF_ABN_INT_EN_REG			0x13008

#define ROCEE_VF_EVENT_INT_EN_REG		0x1300c



#endif /* _HNS_ROCE_COMMON_H */

drivers/infiniband/hw/hns/hns_roce_device.h

+25 −1
Original line number Diff line number Diff line
@@ -134,6 +134,7 @@ enum hns_roce_event { 
	HNS_ROCE_EVENT_TYPE_DB_OVERFLOW               = 0x12,

	HNS_ROCE_EVENT_TYPE_MB                        = 0x13,

	HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW              = 0x14,

	HNS_ROCE_EVENT_TYPE_FLR			      = 0x15,

};



/* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
@@ -541,6 +542,26 @@ struct hns_roce_eq { 
	int				log_page_size;

	int				cons_index;

	struct hns_roce_buf_list	*buf_list;

	int				over_ignore;

	int				coalesce;

	int				arm_st;

	u64				eqe_ba;

	int				eqe_ba_pg_sz;

	int				eqe_buf_pg_sz;

	int				hop_num;

	u64				*bt_l0;	/* Base address table for L0 */

	u64				**bt_l1; /* Base address table for L1 */

	u64				**buf;

	dma_addr_t			l0_dma;

	dma_addr_t			*l1_dma;

	dma_addr_t			*buf_dma;

	u32				l0_last_num; /* L0 last chunk num */

	u32				l1_last_num; /* L1 last chunk num */

	int				eq_max_cnt;

	int				eq_period;

	int				shift;

	dma_addr_t			cur_eqe_ba;

	dma_addr_t			nxt_eqe_ba;

};



struct hns_roce_eq_table {
@@ -571,7 +592,7 @@ struct hns_roce_caps { 
	u32		min_wqes;

	int		reserved_cqs;

	int		num_aeq_vectors;	/* 1 */

	int		num_comp_vectors;	/* 32 ceq */

	int		num_comp_vectors;

	int		num_other_vectors;

	int		num_mtpts;

	u32		num_mtt_segs;
@@ -617,6 +638,9 @@ struct hns_roce_caps { 
	u32		cqe_ba_pg_sz;

	u32		cqe_buf_pg_sz;

	u32		cqe_hop_num;

	u32		eqe_ba_pg_sz;

	u32		eqe_buf_pg_sz;

	u32		eqe_hop_num;

	u32		chunk_sz;	/* chunk size in non multihop mode*/

	u64		flags;

};