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Commit a49479c9 authored by Anant Goel's avatar Anant Goel
Browse files

ARM: dts: msm: Update camera SIDs and clock rates for SA8195P 



Provide updated nodes for the camera SIDs and clock rates as
they have changed for the SA8195P target.

Change-Id: I610f8417585451ceb3fdb8eb68662469a054ec8a
Signed-off-by: default avatarAnant Goel <anantg@codeaurora.org>
parent ed316bc4

arch/arm64/boot/dts/qcom/sa8195p.dtsi

+74 −0
Original line number Diff line number Diff line
@@ -105,4 +105,78 @@ 
			qcom,iova-mapping = <0x80000000 0x40000000>;

		};

	};



	qcom,cam_smmu {

		msm_cam_smmu_ife {

			iommus = <&apps_smmu 0xAA0 0x4E0>,

				<&apps_smmu 0xA20 0x4E0>,

				<&apps_smmu 0xA00 0x4E0>,

				<&apps_smmu 0xA80 0x4E0>,

				<&apps_smmu 0xEA0 0x4E0>,

				<&apps_smmu 0xE20 0x4E0>,

				<&apps_smmu 0xE00 0x4E0>,

				<&apps_smmu 0xE80 0x4E0>;

		};



		msm_cam_smmu_jpeg {

			iommus = <&apps_smmu 0x2100 0x20>,

				<&apps_smmu 0x2120 0x20>;

		};



		msm_cam_smmu_icp {

			iommus = <&apps_smmu 0x2042 0x0>,

				<&apps_smmu 0x2080 0x320>,

				<&apps_smmu 0x20A0 0x320>,

				<&apps_smmu 0x2380 0x320>,

				<&apps_smmu 0x23A0 0x320>,

				<&apps_smmu 0x20C0 0x300>,

				<&apps_smmu 0x23C0 0x300>;

		};



		msm_cam_smmu_fd {

			iommus = <&apps_smmu 0x2140 0x20>,

				<&apps_smmu 0x2160 0x20>;

		};



		msm_cam_smmu_lrme {

			iommus = <&apps_smmu 0x20e0 0x300>,

				<&apps_smmu 0x23E0 0x300>;

		};

	};



	cam_csid0 {

		clock-rates =

			<400000000 0 0 0 400000000 0 0>,

			<400000000 0 0 0 558000000 0 0>,

			<480000000 0 0 0 637000000 0 0>,

			<600000000 0 0 0 760000000 0 0>;

		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";

	};



	cam_csid1 {

		clock-rates =

			<400000000 0 0 0 400000000 0 0>,

			<400000000 0 0 0 558000000 0 0>,

			<480000000 0 0 0 637000000 0 0>,

			<600000000 0 0 0 760000000 0 0>;

		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";

	};



	cam_vfe0 {

		clock-rates =

			<400000000 0 0>,

			<558000000 0 0>,

			<637000000 0 0>,

			<760000000 0 0>;

		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";

	};



	cam_vfe1 {

		clock-rates =

			<400000000 0 0>,

			<558000000 0 0>,

			<637000000 0 0>,

			<760000000 0 0>;

		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";

	};

};