Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a42a5719 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Fix watermark code for BDW 



Looks like I forgot to update the ILK/SNB/IVB watermark patches to deal
with BDW. Add the relevant BDW checks to make sure we take the HSW
codepaths on BDW as well.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 38cc1daf

drivers/gpu/drm/i915/intel_pm.c

+7 −7
Original line number Diff line number Diff line
@@ -2012,7 +2012,7 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5]) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (IS_HASWELL(dev)) {

	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {

		uint64_t sskpd = I915_READ64(MCH_SSKPD);



		wm[0] = (sskpd >> 56) & 0xFF;
@@ -2060,7 +2060,7 @@ static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) 
static int ilk_wm_max_level(const struct drm_device *dev)

{

	/* how many WM levels are we expecting */

	if (IS_HASWELL(dev))

	if (IS_HASWELL(dev) || IS_BROADWELL(dev))

		return 4;

	else if (INTEL_INFO(dev)->gen >= 6)

		return 3;
@@ -2179,7 +2179,7 @@ static bool intel_compute_pipe_wm(struct drm_crtc *crtc, 
		ilk_compute_wm_level(dev_priv, level, params,

				     &pipe_wm->wm[level]);



	if (IS_HASWELL(dev))

	if (IS_HASWELL(dev) || IS_BROADWELL(dev))

		pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);



	/* At least LP0 must be valid */
@@ -2274,7 +2274,7 @@ static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (IS_HASWELL(dev))

	if (IS_HASWELL(dev) || IS_BROADWELL(dev))

		return 2 * level;

	else

		return dev_priv->wm.pri_latency[level];
@@ -2489,7 +2489,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv, 
		I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);



	if (dirty & WM_DIRTY_DDB) {

		if (IS_HASWELL(dev)) {

		if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {

			val = I915_READ(WM_MISC);

			if (results->partitioning == INTEL_DDB_PART_1_2)

				val &= ~WM_MISC_DATA_PARTITION_5_6;
@@ -2628,7 +2628,7 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) 
	};



	hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);

	if (IS_HASWELL(dev))

	if (IS_HASWELL(dev) || IS_BROADWELL(dev))

		hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));



	if (intel_crtc_active(crtc)) {
@@ -2675,7 +2675,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev) 
	hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);

	hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);



	if (IS_HASWELL(dev))

	if (IS_HASWELL(dev) || IS_BROADWELL(dev))

		hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?

			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;

	else if (IS_IVYBRIDGE(dev))