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Commit a2661add authored by Veera Vegivada's avatar Veera Vegivada
Browse files

clk: qcom: Reconfigure trion and regera PLL during set_rate 



During set_rate read the L value to determine
if the configuration is required again, otherwise the
PLL would fail to lock or enable due to lost/missing
values.

Change-Id: Iec4f85e5e2a2faaa956020da91965254b45e5eaf
Signed-off-by: default avatarVeera Vegivada <vvegivad@codeaurora.org>
parent c419b20c

drivers/clk/qcom/clk-alpha-pll.c

+48 −3
Original line number Diff line number Diff line
@@ -954,7 +954,8 @@ static int clk_trion_pll_enable(struct clk_hw *hw) 
			pr_err("Failed to configure %s\n", clk_hw_get_name(hw));

			return ret;

		}

		pr_warn("PLL configuration lost, reconfiguration of PLL done.\n");

		pr_warn("%s: PLL configuration lost, reconfiguration of PLL done.\n",

				clk_hw_get_name(hw));

	}



	/* Set operation mode to RUN */
@@ -1069,10 +1070,34 @@ static int clk_trion_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	unsigned long rrate;

	u32 regval, l, off = pll->offset;

	u32 regval, l, off = pll->offset, cal_val;

	u64 a;

	int ret;



	ret = regmap_read(pll->clkr.regmap, pll->offset + PLL_L_VAL, &l);

	if (ret)

		return ret;



	ret = regmap_read(pll->clkr.regmap, pll->offset + TRION_PLL_CAL_L_VAL,

				&cal_val);

	if (ret)

		return ret;



	/* PLL has lost it's L or CAL value, needs reconfiguration */

	if (!l || !cal_val)

		pll->inited = false;



	if (unlikely(!pll->inited)) {

		ret = clk_trion_pll_configure(pll, pll->clkr.regmap,

						pll->config);

		if (ret) {

			pr_err("Failed to configure %s\n", clk_hw_get_name(hw));

			return ret;

		}

		pr_warn("%s: PLL configuration lost, reconfiguration of PLL done.\n",

				clk_hw_get_name(hw));

	}



	rrate = alpha_pll_round_rate(pll, rate, prate, &l, &a);

	/*

	 * Due to a limited number of bits for fractional rate programming, the
@@ -1246,7 +1271,8 @@ static int clk_regera_pll_enable(struct clk_hw *hw) 
			pr_err("Failed to configure %s\n", clk_hw_get_name(hw));

			return ret;

		}

		pr_warn("PLL configuration lost, reconfiguration of PLL done.\n");

		pr_warn("%s: PLL configuration lost, reconfiguration of PLL done.\n",

				clk_hw_get_name(hw));

	}



	/* Get the PLL out of bypass mode */
@@ -1338,6 +1364,25 @@ static int clk_regera_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
	u64 a;

	int ret;



	ret = regmap_read(pll->clkr.regmap, off + PLL_L_VAL, &l);

	if (ret)

		return ret;



	/* PLL has lost it's L value, needs reconfiguration */

	if (!l)

		pll->inited = false;



	if (unlikely(!pll->inited)) {

		ret = clk_regera_pll_configure(pll, pll->clkr.regmap,

						pll->config);

		if (ret) {

			pr_err("Failed to configure %s\n", clk_hw_get_name(hw));

			return ret;

		}

		pr_warn("%s: PLL configuration lost, reconfiguration of PLL done.\n",

				clk_hw_get_name(hw));

	}



	rrate = alpha_pll_round_rate(pll, rate, prate, &l, &a);

	/*

	 * Due to a limited number of bits for fractional rate programming, the