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Commit a2546b8b authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "defconfig: sm6150: Enable clock controller drivers for SM6150"

parents 37c29e02 54a6f1a1

arch/arm64/boot/dts/qcom/sm6150-gdsc.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -159,7 +159,7 @@ 


	/* GDSCs in Display CC */

	mdss_core_gdsc: qcom,gdsc@af03000 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "mdss_core_gdsc";

		reg = <0xaf03000 0x4>;

		qcom,poll-cfg-gdscr;

arch/arm64/boot/dts/qcom/sm6150.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -773,9 +773,11 @@ 
		#reset-cells = <1>;

	};



	clock_dispcc: qcom,dispcc {

		compatible = "qcom,dummycc";

		clock-output-names = "dispcc_clocks";

	clock_dispcc: qcom,dispcc@af00000 {

		compatible = "qcom,dispcc-sm6150", "syscon";

		reg = <0xaf00000 0x20000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

arch/arm64/configs/vendor/sdmsteppe-perf_defconfig

+2 −0
Original line number Diff line number Diff line
@@ -465,6 +465,8 @@ CONFIG_MSM_GPUCC_SM8150=y 
CONFIG_MSM_GCC_SM6150=y

CONFIG_MSM_GPUCC_SM6150=y

CONFIG_MSM_VIDEOCC_SM6150=y

CONFIG_MSM_CAMCC_SM6150=y

CONFIG_MSM_DISPCC_SM6150=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_QCOM_APCS_IPC=y

arch/arm64/configs/vendor/sdmsteppe_defconfig

+2 −0
Original line number Diff line number Diff line
@@ -482,6 +482,8 @@ CONFIG_MSM_GPUCC_SM8150=y 
CONFIG_MSM_GCC_SM6150=y

CONFIG_MSM_GPUCC_SM6150=y

CONFIG_MSM_VIDEOCC_SM6150=y

CONFIG_MSM_CAMCC_SM6150=y

CONFIG_MSM_DISPCC_SM6150=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_QCOM_APCS_IPC=y