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Commit a20a0e41 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: pcie: add support for configurable PCIe core preset"

parents 7ef1bf17 19c0876d

arch/arm64/boot/dts/qcom/qcs405-pcie.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ 
		qcom,phy-status-offset = <0x3c>;

		qcom,phy-status-bit = <0>;

		qcom,phy-power-down-offset = <0x98>;

		qcom,core-preset = <0x77777777>;

		qcom,boot-option = <0x1>;

		qcom,keep-powerdown-phy;

		qcom,no-l0s-supported;

arch/arm64/boot/dts/qcom/sa6155-pcie.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -151,6 +151,7 @@ 
		qcom,phy-status-offset = <0x974>;

		qcom,phy-status-bit = <6>;

		qcom,phy-power-down-offset = <0x804>;

		qcom,core-preset = <0x77777777>;



		qcom,boot-option = <0x1>;

arch/arm64/boot/dts/qcom/sa8155.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -94,11 +94,13 @@ 
	qcom,no-l1-supported;

	qcom,no-l1ss-supported;

	qcom,no-aux-clk-sync;

	qcom,core-preset = <0x77777777>;

};



&pcie1 {

	vreg-1.8-supply = <&pm8150_2_l8>;

	vreg-0.9-supply = <&pm8150_2_l18>;

	qcom,core-preset = <0x77777777>;

};



&pcie_ep {

drivers/pci/host/pci-msm.c

+15 −1
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ 
#define PCIE20_PARF_DBI_BASE_ADDR       0x350

#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x358



#define PCIE_GEN3_PRESET_DEFAULT		0x55555555

#define PCIE_GEN3_SPCIE_CAP			0x0154

#define PCIE_GEN3_GEN2_CTRL			0x080c

#define PCIE_GEN3_RELATED			0x0890
@@ -696,6 +697,7 @@ struct msm_pcie_dev_t { 
	uint32_t			phy_status_offset;

	uint32_t			phy_status_bit;

	uint32_t			phy_power_down_offset;

	uint32_t			core_preset;

	uint32_t			cpl_timeout;

	uint32_t			current_bdf;

	uint32_t			perst_delay_us_min;
@@ -1341,6 +1343,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) 
		dev->phy_status_bit);

	PCIE_DBG_FS(dev, "phy_power_down_offset: 0x%x\n",

		dev->phy_power_down_offset);

	PCIE_DBG_FS(dev, "core_preset: 0x%x\n",

		dev->core_preset);

	PCIE_DBG_FS(dev, "cpl_timeout: 0x%x\n",

		dev->cpl_timeout);

	PCIE_DBG_FS(dev, "current_bdf: 0x%x\n",
@@ -4132,7 +4136,7 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) 
	msm_pcie_write_reg_field(dev->dm_core,

		PCIE_GEN3_MISC_CONTROL, BIT(0), 1);

	msm_pcie_write_reg(dev->dm_core,

		PCIE_GEN3_SPCIE_CAP, 0x77777777);

		PCIE_GEN3_SPCIE_CAP, dev->core_preset);

	msm_pcie_write_reg_field(dev->dm_core,

		PCIE_GEN3_MISC_CONTROL, BIT(0), 0);
@@ -5856,6 +5860,16 @@ static int msm_pcie_probe(struct platform_device *pdev) 
			"RC%d: phy-power-down-offset: 0x%x.\n",

			rc_idx, msm_pcie_dev[rc_idx].phy_power_down_offset);



	msm_pcie_dev[rc_idx].core_preset = 0;

	ret = of_property_read_u32(pdev->dev.of_node,

				"qcom,core-preset",

				&msm_pcie_dev[rc_idx].core_preset);

	if (ret)

		msm_pcie_dev[rc_idx].core_preset = PCIE_GEN3_PRESET_DEFAULT;



	PCIE_DBG(&msm_pcie_dev[rc_idx], "RC%d: core-preset: 0x%x.\n",

		rc_idx, msm_pcie_dev[rc_idx].core_preset);



	msm_pcie_dev[rc_idx].cpl_timeout = 0;

	ret = of_property_read_u32((&pdev->dev)->of_node,

				"qcom,cpl-timeout",