Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a02f83f7 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: qcom: Remove gcc_cpuss_ahb_clk clock for TRINKET"

parents 50b62ed8 60095804

drivers/clk/qcom/gcc-trinket.c

+0 −45
Original line number Diff line number Diff line
@@ -976,31 +976,6 @@ static struct clk_rcg2 gcc_camss_vfe1_clk_src = { 
	},

};



static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	{ }

};



static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {

	.cmd_rcgr = 0x2b13c,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_cpuss_ahb_clk_src",

		.parent_names = gcc_parent_names_0_ao,

		.num_parents = 4,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_cx_ao,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_LOWER] = 19200000,

			[VDD_LOW] = 50000000,

			[VDD_NOMINAL] = 100000000},

	},

};



static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {

	F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),

	F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
@@ -2877,24 +2852,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 
	},

};



static struct clk_branch gcc_cpuss_ahb_clk = {

	.halt_reg = 0x2b000,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x79004,

		.enable_mask = BIT(21),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_cpuss_ahb_clk",

			.parent_names = (const char *[]){

				"gcc_cpuss_ahb_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_cpuss_gnoc_clk = {

	.halt_reg = 0x2b004,

	.halt_check = BRANCH_HALT_VOTED,
@@ -4312,8 +4269,6 @@ static struct clk_regmap *gcc_trinket_clocks[] = { 
	[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,

	[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,

	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,

	[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,

	[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,

	[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,

	[GCC_CPUSS_THROTTLE_CORE_CLK] = &gcc_cpuss_throttle_core_clk.clkr,

	[GCC_CPUSS_THROTTLE_XO_CLK] = &gcc_cpuss_throttle_xo_clk.clkr,

include/dt-bindings/clock/qcom,gcc-trinket.h

+111 −113
Original line number Diff line number Diff line
@@ -118,119 +118,117 @@ 
#define GCC_CE1_AXI_CLK				101

#define GCC_CE1_CLK				102

#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK		103

#define GCC_CPUSS_AHB_CLK			104

#define GCC_CPUSS_AHB_CLK_SRC			105

#define GCC_CPUSS_GNOC_CLK			106

#define GCC_CPUSS_THROTTLE_CORE_CLK		107

#define GCC_CPUSS_THROTTLE_XO_CLK		108

#define GCC_DISP_AHB_CLK			109

#define GCC_DISP_GPLL0_DIV_CLK_SRC		110

#define GCC_DISP_HF_AXI_CLK			111

#define GCC_DISP_THROTTLE_CORE_CLK		112

#define GCC_DISP_XO_CLK				113

#define GCC_GP1_CLK				114

#define GCC_GP1_CLK_SRC				115

#define GCC_GP2_CLK				116

#define GCC_GP2_CLK_SRC				117

#define GCC_GP3_CLK				118

#define GCC_GP3_CLK_SRC				119

#define GCC_GPU_CFG_AHB_CLK			120

#define GCC_GPU_GPLL0_CLK_SRC			121

#define GCC_GPU_GPLL0_DIV_CLK_SRC		122

#define GCC_GPU_MEMNOC_GFX_CLK			123

#define GCC_GPU_SNOC_DVM_GFX_CLK		124

#define GCC_GPU_THROTTLE_CORE_CLK		125

#define GCC_GPU_THROTTLE_XO_CLK			126

#define GCC_MSS_VS_CLK				127

#define GCC_PDM2_CLK				128

#define GCC_PDM2_CLK_SRC			129

#define GCC_PDM_AHB_CLK				130

#define GCC_PDM_XO4_CLK				131

#define GCC_PRNG_AHB_CLK			132

#define GCC_QMIP_CAMERA_NRT_AHB_CLK		133

#define GCC_QMIP_CAMERA_RT_AHB_CLK		134

#define GCC_QMIP_CPUSS_CFG_AHB_CLK		135

#define GCC_QMIP_DISP_AHB_CLK			136

#define GCC_QMIP_GPU_CFG_AHB_CLK		137

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK		138

#define GCC_QUPV3_WRAP0_CORE_2X_CLK		139

#define GCC_QUPV3_WRAP0_CORE_CLK		140

#define GCC_QUPV3_WRAP0_S0_CLK			141

#define GCC_QUPV3_WRAP0_S0_CLK_SRC		142

#define GCC_QUPV3_WRAP0_S1_CLK			143

#define GCC_QUPV3_WRAP0_S1_CLK_SRC		144

#define GCC_QUPV3_WRAP0_S2_CLK			145

#define GCC_QUPV3_WRAP0_S2_CLK_SRC		146

#define GCC_QUPV3_WRAP0_S3_CLK			147

#define GCC_QUPV3_WRAP0_S3_CLK_SRC		148

#define GCC_QUPV3_WRAP0_S4_CLK			149

#define GCC_QUPV3_WRAP0_S4_CLK_SRC		150

#define GCC_QUPV3_WRAP0_S5_CLK			151

#define GCC_QUPV3_WRAP0_S5_CLK_SRC		152

#define GCC_QUPV3_WRAP1_CORE_2X_CLK		153

#define GCC_QUPV3_WRAP1_CORE_CLK		154

#define GCC_QUPV3_WRAP1_S0_CLK			155

#define GCC_QUPV3_WRAP1_S0_CLK_SRC		156

#define GCC_QUPV3_WRAP1_S1_CLK			157

#define GCC_QUPV3_WRAP1_S1_CLK_SRC		158

#define GCC_QUPV3_WRAP1_S2_CLK			159

#define GCC_QUPV3_WRAP1_S2_CLK_SRC		160

#define GCC_QUPV3_WRAP1_S3_CLK			161

#define GCC_QUPV3_WRAP1_S3_CLK_SRC		162

#define GCC_QUPV3_WRAP1_S4_CLK			163

#define GCC_QUPV3_WRAP1_S4_CLK_SRC		164

#define GCC_QUPV3_WRAP1_S5_CLK			165

#define GCC_QUPV3_WRAP1_S5_CLK_SRC		166

#define GCC_QUPV3_WRAP_0_M_AHB_CLK		167

#define GCC_QUPV3_WRAP_0_S_AHB_CLK		168

#define GCC_QUPV3_WRAP_1_M_AHB_CLK		169

#define GCC_QUPV3_WRAP_1_S_AHB_CLK		170

#define GCC_SDCC1_AHB_CLK			171

#define GCC_SDCC1_APPS_CLK			172

#define GCC_SDCC1_APPS_CLK_SRC			173

#define GCC_SDCC1_ICE_CORE_CLK			174

#define GCC_SDCC1_ICE_CORE_CLK_SRC		175

#define GCC_SDCC2_AHB_CLK			176

#define GCC_SDCC2_APPS_CLK			177

#define GCC_SDCC2_APPS_CLK_SRC			178

#define GCC_SYS_NOC_CPUSS_AHB_CLK		179

#define GCC_SYS_NOC_UFS_PHY_AXI_CLK		180

#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK		181

#define GCC_UFS_PHY_AHB_CLK			182

#define GCC_UFS_PHY_AXI_CLK			183

#define GCC_UFS_PHY_AXI_CLK_SRC			184

#define GCC_UFS_PHY_ICE_CORE_CLK		185

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC		186

#define GCC_UFS_PHY_PHY_AUX_CLK			187

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC		188

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK		189

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK		190

#define GCC_UFS_PHY_UNIPRO_CORE_CLK		191

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC		192

#define GCC_USB30_PRIM_MASTER_CLK		193

#define GCC_USB30_PRIM_MASTER_CLK_SRC		194

#define GCC_USB30_PRIM_MOCK_UTMI_CLK		195

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC	196

#define GCC_USB30_PRIM_SLEEP_CLK		197

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC		198

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK		199

#define GCC_USB3_PRIM_PHY_PIPE_CLK		200

#define GCC_VDDA_VS_CLK				201

#define GCC_VDDCX_VS_CLK			202

#define GCC_VDDMX_VS_CLK			203

#define GCC_VIDEO_AHB_CLK			204

#define GCC_VIDEO_AXI0_CLK			205

#define GCC_VIDEO_THROTTLE_CORE_CLK		206

#define GCC_VIDEO_XO_CLK			207

#define GCC_VS_CTRL_AHB_CLK			208

#define GCC_VS_CTRL_CLK				209

#define GCC_VS_CTRL_CLK_SRC			210

#define GCC_VSENSOR_CLK_SRC			211

#define GCC_WCSS_VS_CLK				212

#define GCC_USB3_PRIM_CLKREF_CLK		213

#define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK		214

#define GCC_BIMC_GPU_AXI_CLK			215

#define GCC_UFS_MEM_CLKREF_CLK			216

#define GCC_CPUSS_GNOC_CLK			104

#define GCC_CPUSS_THROTTLE_CORE_CLK		105

#define GCC_CPUSS_THROTTLE_XO_CLK		106

#define GCC_DISP_AHB_CLK			107

#define GCC_DISP_GPLL0_DIV_CLK_SRC		108

#define GCC_DISP_HF_AXI_CLK			109

#define GCC_DISP_THROTTLE_CORE_CLK		110

#define GCC_DISP_XO_CLK				111

#define GCC_GP1_CLK				112

#define GCC_GP1_CLK_SRC				113

#define GCC_GP2_CLK				114

#define GCC_GP2_CLK_SRC				115

#define GCC_GP3_CLK				116

#define GCC_GP3_CLK_SRC				117

#define GCC_GPU_CFG_AHB_CLK			118

#define GCC_GPU_GPLL0_CLK_SRC			119

#define GCC_GPU_GPLL0_DIV_CLK_SRC		120

#define GCC_GPU_MEMNOC_GFX_CLK			121

#define GCC_GPU_SNOC_DVM_GFX_CLK		122

#define GCC_GPU_THROTTLE_CORE_CLK		123

#define GCC_GPU_THROTTLE_XO_CLK			124

#define GCC_MSS_VS_CLK				125

#define GCC_PDM2_CLK				126

#define GCC_PDM2_CLK_SRC			127

#define GCC_PDM_AHB_CLK				128

#define GCC_PDM_XO4_CLK				129

#define GCC_PRNG_AHB_CLK			130

#define GCC_QMIP_CAMERA_NRT_AHB_CLK		131

#define GCC_QMIP_CAMERA_RT_AHB_CLK		132

#define GCC_QMIP_CPUSS_CFG_AHB_CLK		133

#define GCC_QMIP_DISP_AHB_CLK			134

#define GCC_QMIP_GPU_CFG_AHB_CLK		135

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK		136

#define GCC_QUPV3_WRAP0_CORE_2X_CLK		137

#define GCC_QUPV3_WRAP0_CORE_CLK		138

#define GCC_QUPV3_WRAP0_S0_CLK			139

#define GCC_QUPV3_WRAP0_S0_CLK_SRC		140

#define GCC_QUPV3_WRAP0_S1_CLK			141

#define GCC_QUPV3_WRAP0_S1_CLK_SRC		142

#define GCC_QUPV3_WRAP0_S2_CLK			143

#define GCC_QUPV3_WRAP0_S2_CLK_SRC		144

#define GCC_QUPV3_WRAP0_S3_CLK			145

#define GCC_QUPV3_WRAP0_S3_CLK_SRC		146

#define GCC_QUPV3_WRAP0_S4_CLK			147

#define GCC_QUPV3_WRAP0_S4_CLK_SRC		148

#define GCC_QUPV3_WRAP0_S5_CLK			149

#define GCC_QUPV3_WRAP0_S5_CLK_SRC		150

#define GCC_QUPV3_WRAP1_CORE_2X_CLK		151

#define GCC_QUPV3_WRAP1_CORE_CLK		152

#define GCC_QUPV3_WRAP1_S0_CLK			153

#define GCC_QUPV3_WRAP1_S0_CLK_SRC		154

#define GCC_QUPV3_WRAP1_S1_CLK			155

#define GCC_QUPV3_WRAP1_S1_CLK_SRC		156

#define GCC_QUPV3_WRAP1_S2_CLK			157

#define GCC_QUPV3_WRAP1_S2_CLK_SRC		158

#define GCC_QUPV3_WRAP1_S3_CLK			159

#define GCC_QUPV3_WRAP1_S3_CLK_SRC		160

#define GCC_QUPV3_WRAP1_S4_CLK			161

#define GCC_QUPV3_WRAP1_S4_CLK_SRC		162

#define GCC_QUPV3_WRAP1_S5_CLK			163

#define GCC_QUPV3_WRAP1_S5_CLK_SRC		164

#define GCC_QUPV3_WRAP_0_M_AHB_CLK		165

#define GCC_QUPV3_WRAP_0_S_AHB_CLK		166

#define GCC_QUPV3_WRAP_1_M_AHB_CLK		167

#define GCC_QUPV3_WRAP_1_S_AHB_CLK		168

#define GCC_SDCC1_AHB_CLK			169

#define GCC_SDCC1_APPS_CLK			170

#define GCC_SDCC1_APPS_CLK_SRC			171

#define GCC_SDCC1_ICE_CORE_CLK			172

#define GCC_SDCC1_ICE_CORE_CLK_SRC		173

#define GCC_SDCC2_AHB_CLK			174

#define GCC_SDCC2_APPS_CLK			175

#define GCC_SDCC2_APPS_CLK_SRC			176

#define GCC_SYS_NOC_CPUSS_AHB_CLK		177

#define GCC_SYS_NOC_UFS_PHY_AXI_CLK		178

#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK		179

#define GCC_UFS_PHY_AHB_CLK			180

#define GCC_UFS_PHY_AXI_CLK			181

#define GCC_UFS_PHY_AXI_CLK_SRC			182

#define GCC_UFS_PHY_ICE_CORE_CLK		183

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC		184

#define GCC_UFS_PHY_PHY_AUX_CLK			185

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC		186

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK		187

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK		188

#define GCC_UFS_PHY_UNIPRO_CORE_CLK		189

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC		190

#define GCC_USB30_PRIM_MASTER_CLK		191

#define GCC_USB30_PRIM_MASTER_CLK_SRC		192

#define GCC_USB30_PRIM_MOCK_UTMI_CLK		193

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC	194

#define GCC_USB30_PRIM_SLEEP_CLK		195

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC		196

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK		197

#define GCC_USB3_PRIM_PHY_PIPE_CLK		198

#define GCC_VDDA_VS_CLK				199

#define GCC_VDDCX_VS_CLK			200

#define GCC_VDDMX_VS_CLK			201

#define GCC_VIDEO_AHB_CLK			202

#define GCC_VIDEO_AXI0_CLK			203

#define GCC_VIDEO_THROTTLE_CORE_CLK		204

#define GCC_VIDEO_XO_CLK			205

#define GCC_VS_CTRL_AHB_CLK			206

#define GCC_VS_CTRL_CLK				207

#define GCC_VS_CTRL_CLK_SRC			208

#define GCC_VSENSOR_CLK_SRC			209

#define GCC_WCSS_VS_CLK				210

#define GCC_USB3_PRIM_CLKREF_CLK		211

#define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK		212

#define GCC_BIMC_GPU_AXI_CLK			213

#define GCC_UFS_MEM_CLKREF_CLK			214



/* GCC Resets */

#define GCC_QUSB2PHY_PRIM_BCR			0