Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a0144e2a authored by Paul Mackerras's avatar Paul Mackerras Committed by Alexander Graf
Browse files

KVM: PPC: Book3S HV: Store LPCR value for each virtual core 



This adds the ability to have a separate LPCR (Logical Partitioning
Control Register) value relating to a guest for each virtual core,
rather than only having a single value for the whole VM.  This
corresponds to what real POWER hardware does, where there is a LPCR
per CPU thread but most of the fields are required to have the same
value on all active threads in a core.

The per-virtual-core LPCR can be read and written using the
GET/SET_ONE_REG interface.  Userspace can can only modify the
following fields of the LPCR value:

DPFD	Default prefetch depth
ILE	Interrupt little-endian
TC	Translation control (secondary HPT hash group search disable)

We still maintain a per-VM default LPCR value in kvm->arch.lpcr, which
contains bits relating to memory management, i.e. the Virtualized
Partition Memory (VPM) bits and the bits relating to guest real mode.
When this default value is updated, the update needs to be propagated
to the per-vcore values, so we add a kvmppc_update_lpcr() helper to do
that.

Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
[agraf: fix whitespace]
Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
parent 8b75cbbe

Documentation/virtual/kvm/api.txt

+1 −0
Original line number Original line Diff line number Diff line
@@ -1835,6 +1835,7 @@ registers, find a list below: 
  PPC   | KVM_REG_PPC_PID	| 64

  PPC   | KVM_REG_PPC_PID	| 64

  PPC   | KVM_REG_PPC_ACOP	| 64

  PPC   | KVM_REG_PPC_ACOP	| 64

  PPC   | KVM_REG_PPC_VRSAVE	| 32

  PPC   | KVM_REG_PPC_VRSAVE	| 32

  PPC   | KVM_REG_PPC_LPCR	| 64

  PPC   | KVM_REG_PPC_TM_GPR0	| 64

  PPC   | KVM_REG_PPC_TM_GPR0	| 64

          ...

          ...

  PPC   | KVM_REG_PPC_TM_GPR31	| 64

  PPC   | KVM_REG_PPC_TM_GPR31	| 64

arch/powerpc/include/asm/kvm_book3s.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -172,6 +172,8 @@ extern long kvmppc_do_h_remove(struct kvm *kvm, unsigned long flags, 
			unsigned long *hpret);

			unsigned long *hpret);

extern long kvmppc_hv_get_dirty_log(struct kvm *kvm,

extern long kvmppc_hv_get_dirty_log(struct kvm *kvm,

			struct kvm_memory_slot *memslot, unsigned long *map);

			struct kvm_memory_slot *memslot, unsigned long *map);

extern void kvmppc_update_lpcr(struct kvm *kvm, unsigned long lpcr,

			unsigned long mask);





extern void kvmppc_entry_trampoline(void);

extern void kvmppc_entry_trampoline(void);

extern void kvmppc_hv_entry_trampoline(void);

extern void kvmppc_hv_entry_trampoline(void);

arch/powerpc/include/asm/kvm_host.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -290,6 +290,7 @@ struct kvmppc_vcore { 
	u64 preempt_tb;

	u64 preempt_tb;

	struct kvm_vcpu *runner;

	struct kvm_vcpu *runner;

	u64 tb_offset;		/* guest timebase - host timebase */

	u64 tb_offset;		/* guest timebase - host timebase */

	ulong lpcr;

};

};





#define VCORE_ENTRY_COUNT(vc)	((vc)->entry_exit_count & 0xff)

#define VCORE_ENTRY_COUNT(vc)	((vc)->entry_exit_count & 0xff)

arch/powerpc/include/asm/reg.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -284,6 +284,7 @@ 
#define   LPCR_ISL	(1ul << (63-2))

#define   LPCR_ISL	(1ul << (63-2))

#define   LPCR_VC_SH	(63-2)

#define   LPCR_VC_SH	(63-2)

#define   LPCR_DPFD_SH	(63-11)

#define   LPCR_DPFD_SH	(63-11)

#define   LPCR_DPFD	(7ul << LPCR_DPFD_SH)

#define   LPCR_VRMASD	(0x1ful << (63-16))

#define   LPCR_VRMASD	(0x1ful << (63-16))

#define   LPCR_VRMA_L	(1ul << (63-12))

#define   LPCR_VRMA_L	(1ul << (63-12))

#define   LPCR_VRMA_LP0	(1ul << (63-15))

#define   LPCR_VRMA_LP0	(1ul << (63-15))
@@ -300,6 +301,7 @@ 
#define     LPCR_PECE2	0x00001000	/* machine check etc can cause exit */

#define     LPCR_PECE2	0x00001000	/* machine check etc can cause exit */

#define   LPCR_MER	0x00000800	/* Mediated External Exception */

#define   LPCR_MER	0x00000800	/* Mediated External Exception */

#define   LPCR_MER_SH	11

#define   LPCR_MER_SH	11

#define   LPCR_TC      0x00000200	/* Translation control */

#define   LPCR_LPES    0x0000000c

#define   LPCR_LPES    0x0000000c

#define   LPCR_LPES0   0x00000008      /* LPAR Env selector 0 */

#define   LPCR_LPES0   0x00000008      /* LPAR Env selector 0 */

#define   LPCR_LPES1   0x00000004      /* LPAR Env selector 1 */

#define   LPCR_LPES1   0x00000004      /* LPAR Env selector 1 */
@@ -421,6 +423,7 @@ 
#define	 HID4_RMLS2_SH	 (63 - 2)	/* Real mode limit bottom 2 bits */

#define	 HID4_RMLS2_SH	 (63 - 2)	/* Real mode limit bottom 2 bits */

#define	 HID4_LPID5_SH	 (63 - 6)	/* partition ID bottom 4 bits */

#define	 HID4_LPID5_SH	 (63 - 6)	/* partition ID bottom 4 bits */

#define	 HID4_RMOR_SH	 (63 - 22)	/* real mode offset (16 bits) */

#define	 HID4_RMOR_SH	 (63 - 22)	/* real mode offset (16 bits) */

#define  HID4_RMOR	 (0xFFFFul << HID4_RMOR_SH)

#define  HID4_LPES1	 (1 << (63-57))	/* LPAR env. sel. bit 1 */

#define  HID4_LPES1	 (1 << (63-57))	/* LPAR env. sel. bit 1 */

#define  HID4_RMLS0_SH	 (63 - 58)	/* Real mode limit top bit */

#define  HID4_RMLS0_SH	 (63 - 58)	/* Real mode limit top bit */

#define	 HID4_LPID1_SH	 0		/* partition ID top 2 bits */

#define	 HID4_LPID1_SH	 0		/* partition ID top 2 bits */

arch/powerpc/include/uapi/asm/kvm.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -533,6 +533,7 @@ struct kvm_get_htab_header { 
#define KVM_REG_PPC_ACOP	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3)

#define KVM_REG_PPC_ACOP	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3)





#define KVM_REG_PPC_VRSAVE	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4)

#define KVM_REG_PPC_VRSAVE	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4)

#define KVM_REG_PPC_LPCR	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb5)





/* Transactional Memory checkpointed state:

/* Transactional Memory checkpointed state:

 * This is all GPRs, all VSX regs and a subset of SPRs

 * This is all GPRs, all VSX regs and a subset of SPRs