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Commit 9fc310f4 authored by Chandana Kishori Chiluveru's avatar Chandana Kishori Chiluveru
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ARM: dts: msm: Update QUSB PHY BIAS_CTRL2 parameter on sdmmagpie 



Currently QUSB phy PLL_BIAS_CONTROL_2 register value is overriding
in driver to 0x28. For better USB compliance results update QUSB PHY
BIAS_2 value to 0x22 as per HPG for both device and host modes.

Change-Id: I85d6350ae68877ab347ba0acda287ba33805422f
Signed-off-by: default avatarChandana Kishori Chiluveru <cchiluve@codeaurora.org>
parent 460b918c

arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi

+3 −4
Original line number Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -143,7 +143,6 @@ 
		vdd-supply = <&pm6150_l4>;

		vdda18-supply = <&pm6150_l11>;

		vdda33-supply = <&pm6150_l17>;

		qcom,override-bias-ctrl2;

		qcom,vdd-voltage-level = <0 880000 880000>;

		qcom,qusb-phy-reg-offset =

			<0x240 /* QUSB2PHY_PORT_TUNE1 */
@@ -166,7 +165,7 @@ 
			    0x0a 0x184 /* PLL_LOCK_DELAY */

			    0x19 0xb4  /* PLL_DIGITAL_TIMERS_TWO */

			    0x40 0x194 /* PLL_BIAS_CONTROL_1 */

			    0x20 0x198 /* PLL_BIAS_CONTROL_2 */

			    0x22 0x198 /* PLL_BIAS_CONTROL_2 */

			    0x21 0x214 /* PWR_CTRL2 */

			    0x08 0x220 /* IMP_CTRL1 */

			    0x58 0x224 /* IMP_CTRL2 */
@@ -187,7 +186,7 @@ 
			    0x0a 0x184 /* PLL_LOCK_DELAY */

			    0x19 0xb4  /* PLL_DIGITAL_TIMERS_TWO */

			    0x40 0x194 /* PLL_BIAS_CONTROL_1 */

			    0x20 0x198 /* PLL_BIAS_CONTROL_2 */

			    0x22 0x198 /* PLL_BIAS_CONTROL_2 */

			    0x21 0x214 /* PWR_CTRL2 */

			    0x08 0x220 /* IMP_CTRL1 */

			    0x58 0x224 /* IMP_CTRL2 */