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Commit 9fc15f5f authored by Nicolai Hähnle's avatar Nicolai Hähnle Committed by Alex Deucher
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drm/amdgpu: fix user fence write race condition 



The buffer object backing the user fence is reserved using the non-user
fence, i.e., as soon as the non-user fence is signaled, the user fence
buffer object can be moved or even destroyed.

Therefore, emit the user fence first.

Both fences have the same cache invalidation behavior, so this should
have no user-visible effect.

Signed-off-by: default avatarNicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 860c15e9

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

+6 −6
Original line number Diff line number Diff line
@@ -231,6 +231,12 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
	if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE)

		fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY;



	/* wrap the last IB with fence */

	if (job && job->uf_addr) {

		amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,

				       fence_flags | AMDGPU_FENCE_FLAG_64BIT);

	}



	r = amdgpu_fence_emit(ring, f, fence_flags);

	if (r) {

		dev_err(adev->dev, "failed to emit fence (%d)\n", r);
@@ -243,12 +249,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
	if (ring->funcs->insert_end)

		ring->funcs->insert_end(ring);



	/* wrap the last IB with fence */

	if (job && job->uf_addr) {

		amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,

				       fence_flags | AMDGPU_FENCE_FLAG_64BIT);

	}



	if (patch_offset != ~0 && ring->funcs->patch_cond_exec)

		amdgpu_ring_patch_cond_exec(ring, patch_offset);