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Commit 9dc0ddee authored by Fabrizio Castro's avatar Fabrizio Castro Committed by Geert Uytterhoeven
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clk: renesas: cpg-mssr: Add du1 clock to R8A7745 



Signed-off-by: default avatarFabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das@bp.renesas.com>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent d454cecc

drivers/clk/renesas/r8a7745-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -129,6 +129,7 @@ static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = { 
	DEF_MOD("scif2",		 719,	R8A7745_CLK_P),

	DEF_MOD("scif1",		 720,	R8A7745_CLK_P),

	DEF_MOD("scif0",		 721,	R8A7745_CLK_P),

	DEF_MOD("du1",			 723,	R8A7745_CLK_ZX),

	DEF_MOD("du0",			 724,	R8A7745_CLK_ZX),

	DEF_MOD("ipmmu-sgx",		 800,	R8A7745_CLK_ZX),

	DEF_MOD("vin1",			 810,	R8A7745_CLK_ZG),