drivers: soc: qcom: pm: Add legacy PM and Warmboot set address API support

* MSM PM

PM is the low power management device for MSM (Snapdragon class) chipsets.

This device sets up different components to do low power modes and registers with

the kernel to be notified of idle and suspend states and when called, follows

through the set of instructions in putting the application cores to the lowest

power mode possible.

The PC debug counter reserves 16 registers in the IMEM memory space which maintains

a count on the state of power collapse on each core. This count will be useful to

debug the power collapse state on each core.

The required properties for PM are:

- compatible: "qcom,pm"

The optional properties are:

- reg: physical IMEM address reserved for PC counters and the size

- qcom,use-sync-timer: Indicates whether the target uses the synchronized QTimer.

- qcom,synced-clocks: Indicates that all cpus running off a single clock source and to

	instantiate the necessary clock source.

- qcom,pc-resets-timer: Indicates that the timer gets reset during power collapse.

- qcom,tz-flushes-cache: Indicates that TZ flushes all of the cache during

power collapse. MSM PM can decide to not perform cache flush operations to

reduce latency associated with L2 PC.

- qcom,saw-turns-off-pll: Indicates that the CPU's PLL can be managed from SAW

	hardware. On such targets software management of PLL is not required. If

	this property is specified then qcom,synced-clocks would be ignored.

- qcom,no-pll-switch-for-retention: Boolean property, to indicate that the cpu

	clock can be sourced even from the HFPLL even when the cpu is in

	retention, and need not be switched to an always on pll. If this flag

	is set then the cpu clock is not ramped down when entering retention or

	ramped up on exiting retention.

Example 1:

qcom,pm@fe800664 {

		compatible = "qcom,pm";

		reg = <0xfe800664 0x40>;

		qcom,use-sync-timer;

	};

Example 2:

qcom,pm@fe800664 {

		compatible = "qcom,pm";

		reg = <0xfe800664 0x40>;

		qcom,saw-turns-off-pll;

	};

* MSM PM SNOC client

MSM PM SNOC client device is used to setup a bus request for 100 Mhz for the

SNOC bus when the Apps cores are active. This bus request helps mitigate the

exit latency from power collapse in cases where there aren't any active bus

requests for SNOC.

This device is dependent on the pm-8x60 device, which configures the low power

mode of respective cores.

The required properties of this device are:

- compatible: qcom,pm-snoc-client

- qcom,msm-bus,name:            String representing the client-name

- qcom,msm-bus,num-cases:       Total number of usecases

- qcom,msm-bus,active-only:     Boolean context flag for requests in active or

                                dual (active & sleep) contex

- qcom,msm-bus,num-paths:       Total number of master-slave pairs

- qcom,msm-bus,vectors-KBps:    Arrays of unsigned integers representing:

                                master-id, slave-id, arbitrated bandwidth

                                in KBps, instantaneous bandwidth in KBps

Example:

	qcom,pm-snoc-client {

		compatible = "qcom,pm-snoc-client";

		qcom,msm-bus,name = "ocimem_snoc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,active-only;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors =

			<22 512 0 0>,

			<22 512 320000 3200000>;

	};

obj-$(CONFIG_MSM_APM)          += apm.o

obj-$(CONFIG_QCOM_SMD_RPM)	+= smd-rpm.o

obj-$(CONFIG_QCOM_SMEM) +=	smem.o

obj-$(CONFIG_MSM_PM_LEGACY) += pm-boot.o msm-pm.o

obj-$(CONFIG_MSM_SPM) += msm-spm.o spm_devices.o

obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o

obj-$(CONFIG_QCOM_SMP2P)	+= smp2p.o

/* Copyright (c) 2007-2009,2012-2014, 2018-2019, The Linux Foundation.

 * All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */

#ifndef _ARCH_ARM_MACH_MSM_IDLE_H_

#define _ARCH_ARM_MACH_MSM_IDLE_H_

#define MAX_CPUS_PER_CLUSTER	4

#define MAX_NUM_CLUSTER	4

#ifndef __ASSEMBLY__

#if defined(CONFIG_CPU_V7) || defined(CONFIG_ARM64)

extern unsigned long msm_pm_boot_vector[MAX_NUM_CLUSTER * MAX_CPUS_PER_CLUSTER];

void msm_pm_boot_entry(void);

#else

static inline void msm_pm_boot_entry(void) {}

#endif

#endif

#endif