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Commit 9c9b415c authored by Ralf Baechle's avatar Ralf Baechle
Browse files

MIPS: Reimplement get_cycles(). 



This essentially reverts commit efb9ca08
(kernel.org) / 58020a106879a8b372068741c81f0015c9b0b96dbv [[MIPS] Change
get_cycles to always return 0.]

Most users of get_cycles() invoke it as a timing interface.  That's why
in modern kernels it was never very much missed for.  /dev/random however
uses get_cycles() in the how the jitter in the interrupt timing contains
some useful entropy.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 69f24d17

arch/mips/include/asm/timex.h

+32 −1
Original line number Diff line number Diff line
@@ -10,7 +10,9 @@ 


#ifdef __KERNEL__



#include <asm/cpu-features.h>

#include <asm/mipsregs.h>

#include <asm/cpu-type.h>



/*

 * This is the clock rate of the i8253 PIT.  A MIPS system may not have
@@ -33,9 +35,38 @@ 


typedef unsigned int cycles_t;



/*

 * On R4000/R4400 before version 5.0 an erratum exists such that if the

 * cycle counter is read in the exact moment that it is matching the

 * compare register, no interrupt will be generated.

 *

 * There is a suggested workaround and also the erratum can't strike if

 * the compare interrupt isn't being used as the clock source device.

 * However for now the implementaton of this function doesn't get these

 * fine details right.

 */

static inline cycles_t get_cycles(void)

{

	return 0;

	switch (boot_cpu_type()) {

	case CPU_R4400PC:

	case CPU_R4400SC:

	case CPU_R4400MC:

		if ((read_c0_prid() & 0xff) >= 0x0050)

			return read_c0_count();

		break;



        case CPU_R4000PC:

        case CPU_R4000SC:

        case CPU_R4000MC:

		break;



	default:

		if (cpu_has_counter)

			return read_c0_count();

		break;

	}



	return 0;	/* no usable counter */

}



#endif /* __KERNEL__ */