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Commit 9c98ba3f authored by Mark Gross's avatar Mark Gross Committed by Greg Kroah-Hartman
Browse files

x86/cpu: Add 'table' argument to cpu_matches() 



commit 93920f61c2ad7edb01e63323832585796af75fc9 upstream

To make cpu_matches() reusable for other matching tables, have it take a
pointer to a x86_cpu_id table as an argument.

 [ bp: Flip arguments order. ]

Signed-off-by: default avatarMark Gross <mgross@linux.intel.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarJosh Poimboeuf <jpoimboe@redhat.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent ae585de4

arch/x86/kernel/cpu/common.c

+13 −10
Original line number Diff line number Diff line
@@ -964,9 +964,9 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 
	{}

};



static bool __init cpu_matches(unsigned long which)

static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)

{

	const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist);

	const struct x86_cpu_id *m = x86_match_cpu(table);



	return m && !!(m->driver_data & which);

}
@@ -986,29 +986,32 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 
	u64 ia32_cap = x86_read_arch_cap_msr();



	/* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */

	if (!cpu_matches(NO_ITLB_MULTIHIT) && !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))

	if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&

	    !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))

		setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);



	if (cpu_matches(NO_SPECULATION))

	if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))

		return;



	setup_force_cpu_bug(X86_BUG_SPECTRE_V1);

	setup_force_cpu_bug(X86_BUG_SPECTRE_V2);



	if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) &&

	if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&

	    !(ia32_cap & ARCH_CAP_SSB_NO) &&

	   !cpu_has(c, X86_FEATURE_AMD_SSB_NO))

		setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);



	if (ia32_cap & ARCH_CAP_IBRS_ALL)

		setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);



	if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) {

	if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&

	    !(ia32_cap & ARCH_CAP_MDS_NO)) {

		setup_force_cpu_bug(X86_BUG_MDS);

		if (cpu_matches(MSBDS_ONLY))

		if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))

			setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);

	}



	if (!cpu_matches(NO_SWAPGS))

	if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))

		setup_force_cpu_bug(X86_BUG_SWAPGS);



	/*
@@ -1026,7 +1029,7 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 
	     (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))

		setup_force_cpu_bug(X86_BUG_TAA);



	if (cpu_matches(NO_MELTDOWN))

	if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))

		return;



	/* Rogue Data Cache Load? No! */
@@ -1035,7 +1038,7 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 


	setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);



	if (cpu_matches(NO_L1TF))

	if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))

		return;



	setup_force_cpu_bug(X86_BUG_L1TF);