Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9c987a33 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Catalin Marinas:

 - add TLB invalidation for page table tear-down which was missed when
   support for CONFIG_HAVE_RCU_TABLE_FREE was added (assuming page table
   freeing was always deferred)

 - use UEFI for system and reset poweroff if available

 - fix asm label placement in relation to the alignment statement

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: put __boot_cpu_mode label after alignment instead of before
  efi/arm64: use UEFI for system reset and poweroff
  arm64: Invalidate the TLB corresponding to intermediate page table levels
parents e6c2d9ce 947bb758

arch/arm64/include/asm/tlb.h

+3 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ static inline void tlb_flush(struct mmu_gather *tlb) 
static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,

				  unsigned long addr)

{

	__flush_tlb_pgtable(tlb->mm, addr);

	pgtable_page_dtor(pte);

	tlb_remove_entry(tlb, pte);

}
@@ -56,6 +57,7 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, 
static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,

				  unsigned long addr)

{

	__flush_tlb_pgtable(tlb->mm, addr);

	tlb_remove_entry(tlb, virt_to_page(pmdp));

}

#endif
@@ -64,6 +66,7 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp, 
static inline void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pudp,

				  unsigned long addr)

{

	__flush_tlb_pgtable(tlb->mm, addr);

	tlb_remove_entry(tlb, virt_to_page(pudp));

}

#endif

arch/arm64/include/asm/tlbflush.h

+13 −0
Original line number Diff line number Diff line
@@ -143,6 +143,19 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end 
		flush_tlb_all();

}



/*

 * Used to invalidate the TLB (walk caches) corresponding to intermediate page

 * table levels (pgd/pud/pmd).

 */

static inline void __flush_tlb_pgtable(struct mm_struct *mm,

				       unsigned long uaddr)

{

	unsigned long addr = uaddr >> 12 | ((unsigned long)ASID(mm) << 48);



	dsb(ishst);

	asm("tlbi	vae1is, %0" : : "r" (addr));

	dsb(ish);

}

/*

 * On AArch64, the cache coherency is handled via the set_pte_at() function.

 */

arch/arm64/kernel/efi.c

+9 −0
Original line number Diff line number Diff line
@@ -354,3 +354,12 @@ void efi_virtmap_unload(void) 
	efi_set_pgd(current->active_mm);

	preempt_enable();

}



/*

 * UpdateCapsule() depends on the system being shutdown via

 * ResetSystem().

 */

bool efi_poweroff_required(void)

{

	return efi_enabled(EFI_RUNTIME_SERVICES);

}

arch/arm64/kernel/head.S

+1 −1
Original line number Diff line number Diff line
@@ -585,8 +585,8 @@ ENDPROC(set_cpu_boot_mode_flag) 
 * zeroing of .bss would clobber it.

 */

	.pushsection	.data..cacheline_aligned

ENTRY(__boot_cpu_mode)

	.align	L1_CACHE_SHIFT

ENTRY(__boot_cpu_mode)

	.long	BOOT_CPU_MODE_EL2

	.long	0

	.popsection

arch/arm64/kernel/process.c

+8 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#include <stdarg.h>



#include <linux/compat.h>

#include <linux/efi.h>

#include <linux/export.h>

#include <linux/sched.h>

#include <linux/kernel.h>
@@ -150,6 +151,13 @@ void machine_restart(char *cmd) 
	local_irq_disable();

	smp_send_stop();



	/*

	 * UpdateCapsule() depends on the system being reset via

	 * ResetSystem().

	 */

	if (efi_enabled(EFI_RUNTIME_SERVICES))

		efi_reboot(reboot_mode, NULL);



	/* Now call the architecture specific reboot code. */

	if (arm_pm_restart)

		arm_pm_restart(reboot_mode, cmd);