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Commit 9c8fb548 authored by Vasanthakumar Thiagarajan's avatar Vasanthakumar Thiagarajan Committed by Kalle Valo
Browse files

ath10k: add cycle/rx_clear counters frequency to hw_params 



The frequency at which cycle/rx_clear counters are running might
change from one target type to another. QCA99X0 is running the
counters at 150Mhz while QCA9888X and QCA6174 are running at 88Mhz.
Add a new entry to hw_params to store the target specific frequency
and use it in msecs conversion. This change fixes inconsistent
channel active/busy time.

Signed-off-by: default avatarVasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
Signed-off-by: default avatarKalle Valo <kvalo@qca.qualcomm.com>
parent 3d2a2e29

drivers/net/wireless/ath/ath10k/core.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -53,6 +53,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.uart_pin = 7,

		.uart_pin = 7,

		.has_shifted_cc_wraparound = true,

		.has_shifted_cc_wraparound = true,

		.otp_exe_param = 0,

		.otp_exe_param = 0,

		.channel_counters_freq_hz = 88000,

		.fw = {

		.fw = {

			.dir = QCA988X_HW_2_0_FW_DIR,

			.dir = QCA988X_HW_2_0_FW_DIR,

			.fw = QCA988X_HW_2_0_FW_FILE,

			.fw = QCA988X_HW_2_0_FW_FILE,
@@ -68,6 +69,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,

		.patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,

		.uart_pin = 6,

		.uart_pin = 6,

		.otp_exe_param = 0,

		.otp_exe_param = 0,

		.channel_counters_freq_hz = 88000,

		.fw = {

		.fw = {

			.dir = QCA6174_HW_2_1_FW_DIR,

			.dir = QCA6174_HW_2_1_FW_DIR,

			.fw = QCA6174_HW_2_1_FW_FILE,

			.fw = QCA6174_HW_2_1_FW_FILE,
@@ -83,6 +85,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,

		.patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,

		.uart_pin = 6,

		.uart_pin = 6,

		.otp_exe_param = 0,

		.otp_exe_param = 0,

		.channel_counters_freq_hz = 88000,

		.fw = {

		.fw = {

			.dir = QCA6174_HW_3_0_FW_DIR,

			.dir = QCA6174_HW_3_0_FW_DIR,

			.fw = QCA6174_HW_3_0_FW_FILE,

			.fw = QCA6174_HW_3_0_FW_FILE,
@@ -98,6 +101,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,

		.patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,

		.uart_pin = 6,

		.uart_pin = 6,

		.otp_exe_param = 0,

		.otp_exe_param = 0,

		.channel_counters_freq_hz = 88000,

		.fw = {

		.fw = {

			/* uses same binaries as hw3.0 */

			/* uses same binaries as hw3.0 */

			.dir = QCA6174_HW_3_0_FW_DIR,

			.dir = QCA6174_HW_3_0_FW_DIR,
@@ -115,6 +119,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.uart_pin = 7,

		.uart_pin = 7,

		.otp_exe_param = 0x00000700,

		.otp_exe_param = 0x00000700,

		.continuous_frag_desc = true,

		.continuous_frag_desc = true,

		.channel_counters_freq_hz = 150000,

		.fw = {

		.fw = {

			.dir = QCA99X0_HW_2_0_FW_DIR,

			.dir = QCA99X0_HW_2_0_FW_DIR,

			.fw = QCA99X0_HW_2_0_FW_FILE,

			.fw = QCA99X0_HW_2_0_FW_FILE,

drivers/net/wireless/ath/ath10k/core.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -609,6 +609,8 @@ struct ath10k { 
		 */

		 */

		bool continuous_frag_desc;

		bool continuous_frag_desc;





		u32 channel_counters_freq_hz;



		struct ath10k_hw_params_fw {

		struct ath10k_hw_params_fw {

			const char *dir;

			const char *dir;

			const char *fw;

			const char *fw;

drivers/net/wireless/ath/ath10k/hw.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -152,6 +152,6 @@ void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 
	cc -= cc_prev - cc_fix;

	cc -= cc_prev - cc_fix;

	rcc -= rcc_prev;

	rcc -= rcc_prev;





	survey->time = CCNT_TO_MSEC(cc);

	survey->time = CCNT_TO_MSEC(ar, cc);

	survey->time_busy = CCNT_TO_MSEC(rcc);

	survey->time_busy = CCNT_TO_MSEC(ar, rcc);

}
 
}

drivers/net/wireless/ath/ath10k/hw.h

+1 −2
Original line number Original line Diff line number Diff line
@@ -552,8 +552,7 @@ enum ath10k_hw_rate_cck { 
#define SCRATCH_3_ADDRESS			ar->regs->scratch_3_address

#define SCRATCH_3_ADDRESS			ar->regs->scratch_3_address

#define CPU_INTR_ADDRESS			0x0010

#define CPU_INTR_ADDRESS			0x0010





/* Cycle counters are running at 88MHz */

#define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)

#define CCNT_TO_MSEC(x) ((x) / 88000)





/* Firmware indications to the Host via SCRATCH_3 register. */

/* Firmware indications to the Host via SCRATCH_3 register. */

#define FW_INDICATOR_ADDRESS			ar->regs->fw_indicator_address

#define FW_INDICATOR_ADDRESS			ar->regs->fw_indicator_address