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Commit 9be67373 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes I937f01e4,I448d8460,I3f5e230b into msm-4.14 

* changes:
  ARM: dts: msm: add default display for SDM855
  drm/msm/dsi-staging: add toggle resync fifo on 7nm PHY
  drm/msm/dsi-staging: toggle resync fifo after clock on
parents 1d9fa62e c232692c

arch/arm64/boot/dts/qcom/sdm855-cdp.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -68,6 +68,21 @@ 
	};

};



&dsi_sharp_4k_dsc_cmd {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";

	qcom,mdss-dsi-bl-min-level = <1>;

	qcom,mdss-dsi-bl-max-level = <4095>;

	qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";

	qcom,panel-mode-gpio = <&tlmm 7 0>;

	qcom,platform-te-gpio = <&tlmm 8 0>;

	qcom,platform-reset-gpio = <&tlmm 6 0>;

};



&dsi_sharp_4k_dsc_cmd_display {

	qcom,dsi-display-active;

};



&ufsphy_mem {

	compatible = "qcom,ufs-phy-qmp-v4";

arch/arm64/boot/dts/qcom/sdm855-mtp.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -72,6 +72,21 @@ 
	};

};



&dsi_sharp_4k_dsc_cmd {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";

	qcom,mdss-dsi-bl-min-level = <1>;

	qcom,mdss-dsi-bl-max-level = <4095>;

	qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";

	qcom,panel-mode-gpio = <&tlmm 7 0>;

	qcom,platform-te-gpio = <&tlmm 8 0>;

	qcom,platform-reset-gpio = <&tlmm 6 0>;

};



&dsi_sharp_4k_dsc_cmd_display {

	qcom,dsi-display-active;

};



&ufsphy_mem {

	compatible = "qcom,ufs-phy-qmp-v4";

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c

+2 −0
Original line number Diff line number Diff line
@@ -215,6 +215,7 @@ static void dsi_catalog_phy_3_0_init(struct dsi_phy_hw *phy) 
		dsi_phy_hw_v3_0_is_lanes_in_ulps;

	phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v3_0;

	phy->ops.phy_lane_reset = dsi_phy_hw_v3_0_lane_reset;

	phy->ops.toggle_resync_fifo = dsi_phy_hw_v3_0_toggle_resync_fifo;

}



/**
@@ -240,6 +241,7 @@ static void dsi_catalog_phy_4_0_init(struct dsi_phy_hw *phy) 
		dsi_phy_hw_v4_0_is_lanes_in_ulps;

	phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v4_0;

	phy->ops.phy_lane_reset = dsi_phy_hw_v4_0_lane_reset;

	phy->ops.toggle_resync_fifo = dsi_phy_hw_v4_0_toggle_resync_fifo;

}



/**

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h

+2 −0
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ bool dsi_phy_hw_v3_0_is_lanes_in_ulps(u32 lanes, u32 ulps_lanes); 
int dsi_phy_hw_timing_val_v3_0(struct dsi_phy_per_lane_cfgs *timing_cfg,

		u32 *timing_val, u32 size);

int dsi_phy_hw_v3_0_lane_reset(struct dsi_phy_hw *phy);

void dsi_phy_hw_v3_0_toggle_resync_fifo(struct dsi_phy_hw *phy);



/* Definitions for 7nm PHY hardware driver */

void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
@@ -117,6 +118,7 @@ bool dsi_phy_hw_v4_0_is_lanes_in_ulps(u32 lanes, u32 ulps_lanes); 
int dsi_phy_hw_timing_val_v4_0(struct dsi_phy_per_lane_cfgs *timing_cfg,

		u32 *timing_val, u32 size);

int dsi_phy_hw_v4_0_lane_reset(struct dsi_phy_hw *phy);

void dsi_phy_hw_v4_0_toggle_resync_fifo(struct dsi_phy_hw *phy);



/* DSI controller common ops */

u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl);

drivers/gpu/drm/msm/dsi-staging/dsi_display.c

+23 −0
Original line number Diff line number Diff line
@@ -1779,6 +1779,20 @@ static int dsi_display_phy_reset_config(struct dsi_display *display, 
	return 0;

}



static void dsi_display_toggle_resync_fifo(struct dsi_display *display)

{

	struct dsi_display_ctrl *ctrl;

	int i;



	if (!display)

		return;



	for (i = 0; i < display->ctrl_count; i++) {

		ctrl = &display->ctrl[i];

		dsi_phy_toggle_resync_fifo(ctrl->phy);

	}

}



static int dsi_display_ctrl_update(struct dsi_display *display)

{

	int rc = 0;
@@ -2609,6 +2623,15 @@ int dsi_post_clkon_cb(void *priv, 
		dsi_display_ctrl_irq_update(display, true);

	}

	if (clk & DSI_LINK_CLK) {

		/*

		 * Toggle the resync FIFO everytime clock changes, except

		 * when cont-splash screen transition is going on.

		 * Toggling resync FIFO during cont splash transition

		 * can lead to blinks on the display.

		 */

		if (!display->is_cont_splash_enabled)

			dsi_display_toggle_resync_fifo(display);



		if (display->ulps_enabled) {

			rc = dsi_display_set_ulps(display, false);

			if (rc) {