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Commit 9be1e477 authored May 13, 2015 by Tuomas Tynkkynen Committed by Thierry Reding Aug 21, 2015

ARM: tegra: Enable the DFLL on the Jetson TK1



Add the board-specific properties of the DFLL for the Jetson TK1 board.
On this board, the DFLL will take control of the sd0 regulator on the
on-board AS3722 PMIC.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

parent bf9d0267

arch/arm/boot/dts/tegra124-jetson-tk1.dts

+8 −1

Original line number	Original line	Diff line number	Diff line
	@@ -1462,7 +1462,7 @@
	vin-ldo9-10-supply = <&vdd_5v0_sys>;		vin-ldo9-10-supply = <&vdd_5v0_sys>;
	vin-ldo11-supply = <&vdd_3v3_run>;		vin-ldo11-supply = <&vdd_3v3_run>;

	sd0 {		vdd_cpu: sd0 {
	regulator-name = "+VDD_CPU_AP";		regulator-name = "+VDD_CPU_AP";
	regulator-min-microvolt = <700000>;		regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1400000>;		regulator-max-microvolt = <1400000>;
	@@ -1694,6 +1694,13 @@
	non-removable;		non-removable;
	};		};

			/* CPU DFLL clock */
			clock@0,70110000 {
			status = "okay";
			vdd-cpu-supply = <&vdd_cpu>;
			nvidia,i2c-fs-rate = <400000>;
			};

	ahub@0,70300000 {		ahub@0,70300000 {
	i2s@0,70301100 {		i2s@0,70301100 {
	status = "okay";		status = "okay";