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Commit 9bc727a9 authored by Yunsheng Lin's avatar Yunsheng Lin Committed by David S. Miller
Browse files

net: hns3: refactor the coalesce related struct 



This patch refoctors the coalesce related struct by introducing
the hns3_enet_coalesce struct, in order to fix the coalesce
configuation lost problem when changing the channel number.

Signed-off-by: default avatarYunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: default avatarPeng Li <lipeng321@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent dd38c726

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

+23 −23
Original line number Diff line number Diff line
@@ -168,8 +168,8 @@ void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 
	 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing

	 */



	if (rl_reg > 0 && !tqp_vector->tx_group.gl_adapt_enable &&

	    !tqp_vector->rx_group.gl_adapt_enable)

	if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&

	    !tqp_vector->rx_group.coal.gl_adapt_enable)

		/* According to the hardware, the range of rl_reg is

		 * 0-59 and the unit is 4.

		 */
@@ -205,17 +205,17 @@ static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 
	 */



	/* Default: enable interrupt coalescing self-adaptive and GL */

	tqp_vector->tx_group.gl_adapt_enable = 1;

	tqp_vector->rx_group.gl_adapt_enable = 1;

	tqp_vector->tx_group.coal.gl_adapt_enable = 1;

	tqp_vector->rx_group.coal.gl_adapt_enable = 1;



	tqp_vector->tx_group.int_gl = HNS3_INT_GL_50K;

	tqp_vector->rx_group.int_gl = HNS3_INT_GL_50K;

	tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;

	tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;



	/* Default: disable RL */

	h->kinfo.int_rl_setting = 0;



	tqp_vector->rx_group.flow_level = HNS3_FLOW_LOW;

	tqp_vector->tx_group.flow_level = HNS3_FLOW_LOW;

	tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;

	tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;

}



static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
@@ -224,9 +224,9 @@ static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 
	struct hnae3_handle *h = priv->ae_handle;



	hns3_set_vector_coalesce_tx_gl(tqp_vector,

				       tqp_vector->tx_group.int_gl);

				       tqp_vector->tx_group.coal.int_gl);

	hns3_set_vector_coalesce_rx_gl(tqp_vector,

				       tqp_vector->rx_group.int_gl);

				       tqp_vector->rx_group.coal.int_gl);

	hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);

}
@@ -2393,12 +2393,12 @@ static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 
	u16 new_int_gl;

	int usecs;



	if (!ring_group->int_gl)

	if (!ring_group->coal.int_gl)

		return false;



	if (ring_group->total_packets == 0) {

		ring_group->int_gl = HNS3_INT_GL_50K;

		ring_group->flow_level = HNS3_FLOW_LOW;

		ring_group->coal.int_gl = HNS3_INT_GL_50K;

		ring_group->coal.flow_level = HNS3_FLOW_LOW;

		return true;

	}
@@ -2408,10 +2408,10 @@ static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 
	 * 20-1249MB/s high      (18000 ints/s)

	 * > 40000pps  ultra     (8000 ints/s)

	 */

	new_flow_level = ring_group->flow_level;

	new_int_gl = ring_group->int_gl;

	new_flow_level = ring_group->coal.flow_level;

	new_int_gl = ring_group->coal.int_gl;

	tqp_vector = ring_group->ring->tqp_vector;

	usecs = (ring_group->int_gl << 1);

	usecs = (ring_group->coal.int_gl << 1);

	bytes_per_usecs = ring_group->total_bytes / usecs;

	/* 1000000 microseconds */

	packets_per_secs = ring_group->total_packets * 1000000 / usecs;
@@ -2458,9 +2458,9 @@ static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 


	ring_group->total_bytes = 0;

	ring_group->total_packets = 0;

	ring_group->flow_level = new_flow_level;

	if (new_int_gl != ring_group->int_gl) {

		ring_group->int_gl = new_int_gl;

	ring_group->coal.flow_level = new_flow_level;

	if (new_int_gl != ring_group->coal.int_gl) {

		ring_group->coal.int_gl = new_int_gl;

		return true;

	}

	return false;
@@ -2472,18 +2472,18 @@ static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 
	struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;

	bool rx_update, tx_update;



	if (rx_group->gl_adapt_enable) {

	if (rx_group->coal.gl_adapt_enable) {

		rx_update = hns3_get_new_int_gl(rx_group);

		if (rx_update)

			hns3_set_vector_coalesce_rx_gl(tqp_vector,

						       rx_group->int_gl);

						       rx_group->coal.int_gl);

	}



	if (tx_group->gl_adapt_enable) {

	if (tx_group->coal.gl_adapt_enable) {

		tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group);

		if (tx_update)

			hns3_set_vector_coalesce_tx_gl(tqp_vector,

						       tx_group->int_gl);

						       tx_group->coal.int_gl);

	}

}

drivers/net/ethernet/hisilicon/hns3/hns3_enet.h

+7 −3
Original line number Diff line number Diff line
@@ -460,15 +460,19 @@ enum hns3_link_mode_bits { 
#define HNS3_INT_RL_MAX			0x00EC

#define HNS3_INT_RL_ENABLE_MASK		0x40



struct hns3_enet_coalesce {

	u16 int_gl;

	u8 gl_adapt_enable;

	enum hns3_flow_level_range flow_level;

};



struct hns3_enet_ring_group {

	/* array of pointers to rings */

	struct hns3_enet_ring *ring;

	u64 total_bytes;	/* total bytes processed this group */

	u64 total_packets;	/* total packets processed this group */

	u16 count;

	enum hns3_flow_level_range flow_level;

	u16 int_gl;

	u8 gl_adapt_enable;

	struct hns3_enet_coalesce coal;

};



struct hns3_enet_tqp_vector {

drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c

+16 −10
Original line number Diff line number Diff line
@@ -905,11 +905,13 @@ static int hns3_get_coalesce_per_queue(struct net_device *netdev, u32 queue, 
	tx_vector = priv->ring_data[queue].ring->tqp_vector;

	rx_vector = priv->ring_data[queue_num + queue].ring->tqp_vector;



	cmd->use_adaptive_tx_coalesce = tx_vector->tx_group.gl_adapt_enable;

	cmd->use_adaptive_rx_coalesce = rx_vector->rx_group.gl_adapt_enable;

	cmd->use_adaptive_tx_coalesce =

			tx_vector->tx_group.coal.gl_adapt_enable;

	cmd->use_adaptive_rx_coalesce =

			rx_vector->rx_group.coal.gl_adapt_enable;



	cmd->tx_coalesce_usecs = tx_vector->tx_group.int_gl;

	cmd->rx_coalesce_usecs = rx_vector->rx_group.int_gl;

	cmd->tx_coalesce_usecs = tx_vector->tx_group.coal.int_gl;

	cmd->rx_coalesce_usecs = rx_vector->rx_group.coal.int_gl;



	cmd->tx_coalesce_usecs_high = h->kinfo.int_rl_setting;

	cmd->rx_coalesce_usecs_high = h->kinfo.int_rl_setting;
@@ -1029,14 +1031,18 @@ static void hns3_set_coalesce_per_queue(struct net_device *netdev, 
	tx_vector = priv->ring_data[queue].ring->tqp_vector;

	rx_vector = priv->ring_data[queue_num + queue].ring->tqp_vector;



	tx_vector->tx_group.gl_adapt_enable = cmd->use_adaptive_tx_coalesce;

	rx_vector->rx_group.gl_adapt_enable = cmd->use_adaptive_rx_coalesce;

	tx_vector->tx_group.coal.gl_adapt_enable =

				cmd->use_adaptive_tx_coalesce;

	rx_vector->rx_group.coal.gl_adapt_enable =

				cmd->use_adaptive_rx_coalesce;



	tx_vector->tx_group.int_gl = cmd->tx_coalesce_usecs;

	rx_vector->rx_group.int_gl = cmd->rx_coalesce_usecs;

	tx_vector->tx_group.coal.int_gl = cmd->tx_coalesce_usecs;

	rx_vector->rx_group.coal.int_gl = cmd->rx_coalesce_usecs;



	hns3_set_vector_coalesce_tx_gl(tx_vector, tx_vector->tx_group.int_gl);

	hns3_set_vector_coalesce_rx_gl(rx_vector, rx_vector->rx_group.int_gl);

	hns3_set_vector_coalesce_tx_gl(tx_vector,

				       tx_vector->tx_group.coal.int_gl);

	hns3_set_vector_coalesce_rx_gl(rx_vector,

				       rx_vector->rx_group.coal.int_gl);



	hns3_set_vector_coalesce_rl(tx_vector, h->kinfo.int_rl_setting);

	hns3_set_vector_coalesce_rl(rx_vector, h->kinfo.int_rl_setting);