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Commit 9b1e14f4 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Pass dev_priv to IS_PINEVIEW() 



Unify our approach to things by passing around dev_priv instead of dev.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1477946245-14134-17-git-send-email-ville.syrjala@linux.intel.com


Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 646d5772

drivers/gpu/drm/i915/i915_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -2735,7 +2735,7 @@ struct drm_i915_cmd_table { 
#define IS_G4X(dev_priv)	((dev_priv)->info.is_g4x)

#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)

#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)

#define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)

#define IS_PINEVIEW(dev_priv)	((dev_priv)->info.is_pineview)

#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)

#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)

#define IS_IVYBRIDGE(dev_priv)	((dev_priv)->info.is_ivybridge)

drivers/gpu/drm/i915/intel_display.c

+9 −10
Original line number Diff line number Diff line
@@ -7721,10 +7721,10 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc, 
				     struct intel_crtc_state *crtc_state,

				     struct dpll *reduced_clock)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	u32 fp, fp2 = 0;



	if (IS_PINEVIEW(dev)) {

	if (IS_PINEVIEW(dev_priv)) {

		fp = pnv_dpll_compute_fp(&crtc_state->dpll);

		if (reduced_clock)

			fp2 = pnv_dpll_compute_fp(reduced_clock);
@@ -8143,8 +8143,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, 
			      struct intel_crtc_state *crtc_state,

			      struct dpll *reduced_clock)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	u32 dpll;

	struct dpll *clock = &crtc_state->dpll;
@@ -8170,7 +8169,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, 
		dpll |= DPLL_SDVO_HIGH_SPEED;



	/* compute bitmask from p1 value */

	if (IS_PINEVIEW(dev))

	if (IS_PINEVIEW(dev_priv))

		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;

	else {

		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
@@ -8191,7 +8190,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, 
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;

		break;

	}

	if (INTEL_INFO(dev)->gen >= 4)

	if (INTEL_GEN(dev_priv) >= 4)

		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);



	if (crtc_state->sdvo_tv_clock)
@@ -8205,7 +8204,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, 
	dpll |= DPLL_VCO_ENABLE;

	crtc_state->dpll_hw_state.dpll = dpll;



	if (INTEL_INFO(dev)->gen >= 4) {

	if (INTEL_GEN(dev_priv) >= 4) {

		u32 dpll_md = (crtc_state->pixel_multiplier - 1)

			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;

		crtc_state->dpll_hw_state.dpll_md = dpll_md;
@@ -11353,7 +11352,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, 
		fp = pipe_config->dpll_hw_state.fp1;



	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;

	if (IS_PINEVIEW(dev)) {

	if (IS_PINEVIEW(dev_priv)) {

		clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;

		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;

	} else {
@@ -11362,7 +11361,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, 
	}



	if (!IS_GEN2(dev_priv)) {

		if (IS_PINEVIEW(dev))

		if (IS_PINEVIEW(dev_priv))

			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>

				DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);

		else
@@ -11384,7 +11383,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, 
			return;

		}



		if (IS_PINEVIEW(dev))

		if (IS_PINEVIEW(dev_priv))

			port_clock = pnv_calc_dpll_params(refclk, &clock);

		else

			port_clock = i9xx_calc_dpll_params(refclk, &clock);

drivers/gpu/drm/i915/intel_pm.c

+4 −5
Original line number Diff line number Diff line
@@ -320,7 +320,6 @@ static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) 


void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)

{

	struct drm_device *dev = &dev_priv->drm;

	u32 val;



	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
@@ -330,7 +329,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) 
	} else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {

		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);

		POSTING_READ(FW_BLC_SELF);

	} else if (IS_PINEVIEW(dev)) {

	} else if (IS_PINEVIEW(dev_priv)) {

		val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;

		val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;

		I915_WRITE(DSPFW3, val);
@@ -7628,7 +7627,7 @@ static void gen3_init_clock_gating(struct drm_device *dev) 
		DSTATE_DOT_CLOCK_GATING;

	I915_WRITE(D_STATE, dstate);



	if (IS_PINEVIEW(dev))

	if (IS_PINEVIEW(dev_priv))

		I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));



	/* IIR "flip pending" means done if this bit is set */
@@ -7744,7 +7743,7 @@ void intel_init_pm(struct drm_device *dev) 
	intel_fbc_init(dev_priv);



	/* For cxsr */

	if (IS_PINEVIEW(dev))

	if (IS_PINEVIEW(dev_priv))

		i915_pineview_get_mem_freq(dev);

	else if (IS_GEN5(dev_priv))

		i915_ironlake_get_mem_freq(dev);
@@ -7778,7 +7777,7 @@ void intel_init_pm(struct drm_device *dev) 
	} else if (IS_VALLEYVIEW(dev_priv)) {

		vlv_setup_wm_latency(dev);

		dev_priv->display.update_wm = vlv_update_wm;

	} else if (IS_PINEVIEW(dev)) {

	} else if (IS_PINEVIEW(dev_priv)) {

		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),

					    dev_priv->is_ddr3,

					    dev_priv->fsb_freq,