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Commit 9b1b1dbd authored by Rishi Gupta's avatar Rishi Gupta Committed by Gerrit - the friendly Code Review server
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ARM: dts: sa2150p: add support for NAND based SOM 



This commit adds initial device tree required for sa2150p
based SOM having NAND storage.

Although the SoC is quad core but it is made to operate
in dual core mode as board's PDN specifications are
exceeded.

Change-Id: Ie32687222e817b325833e55dd9cc16477ced7e5c
Signed-off-by: default avatarRishi Gupta <rishgupt@codeaurora.org>
parent eba978f5

Documentation/devicetree/bindings/arm/msm/msm.txt

+3 −0
Original line number Diff line number Diff line
@@ -115,6 +115,9 @@ SoCs: 
- SA2145P

  compatible = "qcom,sa2145p"



- SA2150P

  compatible = "qcom,sa2150p"



Generic board variants:



- CDP device:

arch/arm64/boot/dts/qcom/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ dtb-$(CONFIG_ARCH_QCS405) += qcs405-iot-sku1.dtb \ 
		qcs407-iot-sku12.dtb \

		sa2150p-ccard-emmc.dtb \

		sa2145p-ccard-nand-dc.dtb \

		sa2150p-ccard-nand-dc.dtb \

		sa2150p-ccard-nand.dtb \

		qcs405-iot-sku13.dtb \

		qcs407-iot-sku13.dtb \

arch/arm64/boot/dts/qcom/sa2150p-ccard-nand-dc.dts

0 → 100644
+98 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



/dts-v1/;



#include "sa2150p-ccard.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. SA2150P CCARD NAND DC";

	compatible = "qcom,sa2150p-ccard", "qcom,qcs405", "qcom,sa2150p",

				"qcom,ccard";

	qcom,board-id = <25 2>, <25 0x102>;



	cpus {

		/delete-node/ cpu@102;

		/delete-node/ cpu@103;



		cpu-map {

			cluster0 {

				/delete-node/ core2;

				/delete-node/ core3;

			};

		};

	};

};



&soc {

	cpuss_dump {

		/delete-node/ qcom,l1_i_cache102;

		/delete-node/ qcom,l1_i_cache103;

		/delete-node/ qcom,l1_d_cache102;

		/delete-node/ qcom,l1_d_cache103;

	};



	qcom,spm@b012000 {

		qcom,cpu-vctl-list = <&CPU0 &CPU1>;

	};



	qcom,lpm-levels {

		qcom,pm-cluster@0{

			qcom,pm-cpu {

				qcom,cpu = <&CPU0 &CPU1>;

			};

		};

	};



	/delete-node/ cti@61ba000;

	/delete-node/ cti@61bb000;

	/delete-node/ etm@61be000;

	/delete-node/ etm@61bf000;



	funnel@61a1000 {

		ports {

			/delete-node/ port@3;

			/delete-node/ port@4;

		};

	};



	/delete-node/ qcom,cpu0-computemon;



	cpu0_computemon: qcom,cpu0-computemon {

		compatible = "qcom,arm-cpu-mon";

		qcom,cpulist = <&CPU0 &CPU1>;

		qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;

		qcom,core-dev-table =

			< 1094400 MHZ_TO_MBPS( 297, 8) >,

			< 1248000 MHZ_TO_MBPS( 597, 8) >,

			< 1401600 MHZ_TO_MBPS( 710, 8) >;

	};

};



&thermal_zones {

	cpuss-max-step {

		cooling-maps {

			/delete-node/ cpu2_cdev;

			/delete-node/ cpu3_cdev;

		};

	};

	/delete-node/ cpuss-2-step;

	/delete-node/ cpuss-3-step;

};



&qnand_1 {

	status = "okay";

};



&sdhc_1 {

	status = "disabled";

};