perf/x86: Rename x86_pmu::er_flags to 'flags' (9a5e3fb5) · Commits · e / devices / android_kernel_xiaomi_nabu

arch/x86/kernel/cpu/perf_event.h

+6 −3

Original line number	Original line	Diff line number	Diff line
	@@ -521,7 +521,7 @@ struct x86_pmu {
	* Extra registers for events		* Extra registers for events
	*/		*/
	struct extra_reg *extra_regs;		struct extra_reg *extra_regs;
	unsigned int er_flags;		unsigned int flags;

	/*		/*
	* Intel host/guest support (KVM)		* Intel host/guest support (KVM)
	@@ -545,8 +545,11 @@ do { \
	x86_pmu.quirks = &__quirk; \		x86_pmu.quirks = &__quirk; \
	} while (0)		} while (0)

	#define ERF_NO_HT_SHARING 1		/*
	#define ERF_HAS_RSP_1 2		* x86_pmu flags
			*/
			#define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */
			#define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */

	#define EVENT_VAR(_id) event_attr_##_id		#define EVENT_VAR(_id) event_attr_##_id
	#define EVENT_PTR(_id) &event_attr_##_id.attr.attr		#define EVENT_PTR(_id) &event_attr_##_id.attr.attr

arch/x86/kernel/cpu/perf_event_intel.c

+12 −12

Original line number	Original line	Diff line number	Diff line
	@@ -1667,7 +1667,7 @@ intel_bts_constraints(struct perf_event *event)

	static int intel_alt_er(int idx)		static int intel_alt_er(int idx)
	{		{
	if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))		if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
	return idx;		return idx;

	if (idx == EXTRA_REG_RSP_0)		if (idx == EXTRA_REG_RSP_0)
	@@ -2250,7 +2250,7 @@ static void intel_pmu_cpu_starting(int cpu)
	if (!cpuc->shared_regs)		if (!cpuc->shared_regs)
	return;		return;

	if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {		if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
	for_each_cpu(i, topology_thread_cpumask(cpu)) {		for_each_cpu(i, topology_thread_cpumask(cpu)) {
	struct intel_shared_regs *pc;		struct intel_shared_regs *pc;

	@@ -2671,7 +2671,7 @@ __init int intel_pmu_init(void)
	x86_pmu.event_constraints = intel_slm_event_constraints;		x86_pmu.event_constraints = intel_slm_event_constraints;
	x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;		x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
	x86_pmu.extra_regs = intel_slm_extra_regs;		x86_pmu.extra_regs = intel_slm_extra_regs;
	x86_pmu.er_flags \|= ERF_HAS_RSP_1;		x86_pmu.flags \|= PMU_FL_HAS_RSP_1;
	pr_cont("Silvermont events, ");		pr_cont("Silvermont events, ");
	break;		break;

	@@ -2689,7 +2689,7 @@ __init int intel_pmu_init(void)
	x86_pmu.enable_all = intel_pmu_nhm_enable_all;		x86_pmu.enable_all = intel_pmu_nhm_enable_all;
	x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;		x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
	x86_pmu.extra_regs = intel_westmere_extra_regs;		x86_pmu.extra_regs = intel_westmere_extra_regs;
	x86_pmu.er_flags \|= ERF_HAS_RSP_1;		x86_pmu.flags \|= PMU_FL_HAS_RSP_1;

	x86_pmu.cpu_events = nhm_events_attrs;		x86_pmu.cpu_events = nhm_events_attrs;

	@@ -2721,8 +2721,8 @@ __init int intel_pmu_init(void)
	else		else
	x86_pmu.extra_regs = intel_snb_extra_regs;		x86_pmu.extra_regs = intel_snb_extra_regs;
	/* all extra regs are per-cpu when HT is on */		/* all extra regs are per-cpu when HT is on */
	x86_pmu.er_flags \|= ERF_HAS_RSP_1;		x86_pmu.flags \|= PMU_FL_HAS_RSP_1;
	x86_pmu.er_flags \|= ERF_NO_HT_SHARING;		x86_pmu.flags \|= PMU_FL_NO_HT_SHARING;

	x86_pmu.cpu_events = snb_events_attrs;		x86_pmu.cpu_events = snb_events_attrs;

	@@ -2756,8 +2756,8 @@ __init int intel_pmu_init(void)
	else		else
	x86_pmu.extra_regs = intel_snb_extra_regs;		x86_pmu.extra_regs = intel_snb_extra_regs;
	/* all extra regs are per-cpu when HT is on */		/* all extra regs are per-cpu when HT is on */
	x86_pmu.er_flags \|= ERF_HAS_RSP_1;		x86_pmu.flags \|= PMU_FL_HAS_RSP_1;
	x86_pmu.er_flags \|= ERF_NO_HT_SHARING;		x86_pmu.flags \|= PMU_FL_NO_HT_SHARING;

	x86_pmu.cpu_events = snb_events_attrs;		x86_pmu.cpu_events = snb_events_attrs;

	@@ -2784,8 +2784,8 @@ __init int intel_pmu_init(void)
	x86_pmu.extra_regs = intel_snbep_extra_regs;		x86_pmu.extra_regs = intel_snbep_extra_regs;
	x86_pmu.pebs_aliases = intel_pebs_aliases_snb;		x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
	/* all extra regs are per-cpu when HT is on */		/* all extra regs are per-cpu when HT is on */
	x86_pmu.er_flags \|= ERF_HAS_RSP_1;		x86_pmu.flags \|= PMU_FL_HAS_RSP_1;
	x86_pmu.er_flags \|= ERF_NO_HT_SHARING;		x86_pmu.flags \|= PMU_FL_NO_HT_SHARING;

	x86_pmu.hw_config = hsw_hw_config;		x86_pmu.hw_config = hsw_hw_config;
	x86_pmu.get_event_constraints = hsw_get_event_constraints;		x86_pmu.get_event_constraints = hsw_get_event_constraints;
	@@ -2817,8 +2817,8 @@ __init int intel_pmu_init(void)
	x86_pmu.extra_regs = intel_snbep_extra_regs;		x86_pmu.extra_regs = intel_snbep_extra_regs;
	x86_pmu.pebs_aliases = intel_pebs_aliases_snb;		x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
	/* all extra regs are per-cpu when HT is on */		/* all extra regs are per-cpu when HT is on */
	x86_pmu.er_flags \|= ERF_HAS_RSP_1;		x86_pmu.flags \|= PMU_FL_HAS_RSP_1;
	x86_pmu.er_flags \|= ERF_NO_HT_SHARING;		x86_pmu.flags \|= PMU_FL_NO_HT_SHARING;

	x86_pmu.hw_config = hsw_hw_config;		x86_pmu.hw_config = hsw_hw_config;
	x86_pmu.get_event_constraints = hsw_get_event_constraints;		x86_pmu.get_event_constraints = hsw_get_event_constraints;