IB/hns: Add driver files for hns RoCE driver (9a443537) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/infiniband/hw/hns/hns_roce_ah.c

0 → 100644

+128 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2016 Hisilicon Limited.
		*
		* This software is available to you under a choice of one of two
		* licenses. You may choose to be licensed under the terms of the GNU
		* General Public License (GPL) Version 2, available from the file
		* COPYING in the main directory of this source tree, or the
		* OpenIB.org BSD license below:
		*
		* Redistribution and use in source and binary forms, with or
		* without modification, are permitted provided that the following
		* conditions are met:
		*
		* - Redistributions of source code must retain the above
		* copyright notice, this list of conditions and the following
		* disclaimer.
		*
		* - Redistributions in binary form must reproduce the above
		* copyright notice, this list of conditions and the following
		* disclaimer in the documentation and/or other materials
		* provided with the distribution.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
		* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
		* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
		* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
		* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
		* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
		* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
		* SOFTWARE.
		*/

		#include <linux/platform_device.h>
		#include <rdma/ib_addr.h>
		#include <rdma/ib_cache.h>
		#include "hns_roce_device.h"

		#define HNS_ROCE_PORT_NUM_SHIFT 24
		#define HNS_ROCE_VLAN_SL_BIT_MASK 7
		#define HNS_ROCE_VLAN_SL_SHIFT 13

		struct ib_ah hns_roce_create_ah(struct ib_pd ibpd, struct ib_ah_attr *ah_attr)
		{
		struct hns_roce_dev *hr_dev = to_hr_dev(ibpd->device);
		struct device *dev = &hr_dev->pdev->dev;
		struct ib_gid_attr gid_attr;
		struct hns_roce_ah *ah;
		u16 vlan_tag = 0xffff;
		struct in6_addr in6;
		union ib_gid sgid;
		int ret;

		ah = kzalloc(sizeof(*ah), GFP_ATOMIC);
		if (!ah)
		return ERR_PTR(-ENOMEM);

		/* Get mac address */
		memcpy(&in6, ah_attr->grh.dgid.raw, sizeof(ah_attr->grh.dgid.raw));
		if (rdma_is_multicast_addr(&in6))
		rdma_get_mcast_mac(&in6, ah->av.mac);
		else
		memcpy(ah->av.mac, ah_attr->dmac, sizeof(ah_attr->dmac));

		/* Get source gid */
		ret = ib_get_cached_gid(ibpd->device, ah_attr->port_num,
		ah_attr->grh.sgid_index, &sgid, &gid_attr);
		if (ret) {
		dev_err(dev, "get sgid failed! ret = %d\n", ret);
		kfree(ah);
		return ERR_PTR(ret);
		}

		if (gid_attr.ndev) {
		if (is_vlan_dev(gid_attr.ndev))
		vlan_tag = vlan_dev_vlan_id(gid_attr.ndev);
		dev_put(gid_attr.ndev);
		}

		if (vlan_tag < 0x1000)
		vlan_tag \|= (ah_attr->sl & HNS_ROCE_VLAN_SL_BIT_MASK) <<
		HNS_ROCE_VLAN_SL_SHIFT;

		ah->av.port_pd = cpu_to_be32(to_hr_pd(ibpd)->pdn \| (ah_attr->port_num <<
		HNS_ROCE_PORT_NUM_SHIFT));
		ah->av.gid_index = ah_attr->grh.sgid_index;
		ah->av.vlan = cpu_to_le16(vlan_tag);
		dev_dbg(dev, "gid_index = 0x%x,vlan = 0x%x\n", ah->av.gid_index,
		ah->av.vlan);

		if (ah_attr->static_rate)
		ah->av.stat_rate = IB_RATE_10_GBPS;

		memcpy(ah->av.dgid, ah_attr->grh.dgid.raw, HNS_ROCE_GID_SIZE);
		ah->av.sl_tclass_flowlabel = cpu_to_le32(ah_attr->sl <<
		HNS_ROCE_SL_SHIFT);

		return &ah->ibah;
		}

		int hns_roce_query_ah(struct ib_ah ibah, struct ib_ah_attr ah_attr)
		{
		struct hns_roce_ah *ah = to_hr_ah(ibah);

		memset(ah_attr, 0, sizeof(*ah_attr));

		ah_attr->sl = le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
		HNS_ROCE_SL_SHIFT;
		ah_attr->port_num = le32_to_cpu(ah->av.port_pd) >>
		HNS_ROCE_PORT_NUM_SHIFT;
		ah_attr->static_rate = ah->av.stat_rate;
		ah_attr->ah_flags = IB_AH_GRH;
		ah_attr->grh.traffic_class = le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
		HNS_ROCE_TCLASS_SHIFT;
		ah_attr->grh.flow_label = le32_to_cpu(ah->av.sl_tclass_flowlabel) &
		HNS_ROCE_FLOW_LABLE_MASK;
		ah_attr->grh.hop_limit = ah->av.hop_limit;
		ah_attr->grh.sgid_index = ah->av.gid_index;
		memcpy(ah_attr->grh.dgid.raw, ah->av.dgid, HNS_ROCE_GID_SIZE);

		return 0;
		}

		int hns_roce_destroy_ah(struct ib_ah *ah)
		{
		kfree(to_hr_ah(ah));

		return 0;
		}

drivers/infiniband/hw/hns/hns_roce_alloc.c

0 → 100644

+257 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2016 Hisilicon Limited.
		* Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
		*
		* This software is available to you under a choice of one of two
		* licenses. You may choose to be licensed under the terms of the GNU
		* General Public License (GPL) Version 2, available from the file
		* COPYING in the main directory of this source tree, or the
		* OpenIB.org BSD license below:
		*
		* Redistribution and use in source and binary forms, with or
		* without modification, are permitted provided that the following
		* conditions are met:
		*
		* - Redistributions of source code must retain the above
		* copyright notice, this list of conditions and the following
		* disclaimer.
		*
		* - Redistributions in binary form must reproduce the above
		* copyright notice, this list of conditions and the following
		* disclaimer in the documentation and/or other materials
		* provided with the distribution.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
		* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
		* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
		* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
		* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
		* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
		* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
		* SOFTWARE.
		*/

		#include <linux/platform_device.h>
		#include "hns_roce_device.h"

		int hns_roce_bitmap_alloc(struct hns_roce_bitmap bitmap, unsigned long obj)
		{
		int ret = 0;

		spin_lock(&bitmap->lock);
		*obj = find_next_zero_bit(bitmap->table, bitmap->max, bitmap->last);
		if (*obj >= bitmap->max) {
		bitmap->top = (bitmap->top + bitmap->max + bitmap->reserved_top)
		& bitmap->mask;
		*obj = find_first_zero_bit(bitmap->table, bitmap->max);
		}

		if (*obj < bitmap->max) {
		set_bit(*obj, bitmap->table);
		bitmap->last = (*obj + 1);
		if (bitmap->last == bitmap->max)
		bitmap->last = 0;
		*obj \|= bitmap->top;
		} else {
		ret = -1;
		}

		spin_unlock(&bitmap->lock);

		return ret;
		}

		void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj)
		{
		hns_roce_bitmap_free_range(bitmap, obj, 1);
		}

		int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
		int align, unsigned long *obj)
		{
		int ret = 0;
		int i;

		if (likely(cnt == 1 && align == 1))
		return hns_roce_bitmap_alloc(bitmap, obj);

		spin_lock(&bitmap->lock);

		*obj = bitmap_find_next_zero_area(bitmap->table, bitmap->max,
		bitmap->last, cnt, align - 1);
		if (*obj >= bitmap->max) {
		bitmap->top = (bitmap->top + bitmap->max + bitmap->reserved_top)
		& bitmap->mask;
		*obj = bitmap_find_next_zero_area(bitmap->table, bitmap->max, 0,
		cnt, align - 1);
		}

		if (*obj < bitmap->max) {
		for (i = 0; i < cnt; i++)
		set_bit(*obj + i, bitmap->table);

		if (*obj == bitmap->last) {
		bitmap->last = (*obj + cnt);
		if (bitmap->last >= bitmap->max)
		bitmap->last = 0;
		}
		*obj \|= bitmap->top;
		} else {
		ret = -1;
		}

		spin_unlock(&bitmap->lock);

		return ret;
		}

		void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
		unsigned long obj, int cnt)
		{
		int i;

		obj &= bitmap->max + bitmap->reserved_top - 1;

		spin_lock(&bitmap->lock);
		for (i = 0; i < cnt; i++)
		clear_bit(obj + i, bitmap->table);

		bitmap->last = min(bitmap->last, obj);
		bitmap->top = (bitmap->top + bitmap->max + bitmap->reserved_top)
		& bitmap->mask;
		spin_unlock(&bitmap->lock);
		}

		int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
		u32 reserved_bot, u32 reserved_top)
		{
		u32 i;

		if (num != roundup_pow_of_two(num))
		return -EINVAL;

		bitmap->last = 0;
		bitmap->top = 0;
		bitmap->max = num - reserved_top;
		bitmap->mask = mask;
		bitmap->reserved_top = reserved_top;
		spin_lock_init(&bitmap->lock);
		bitmap->table = kcalloc(BITS_TO_LONGS(bitmap->max), sizeof(long),
		GFP_KERNEL);
		if (!bitmap->table)
		return -ENOMEM;

		for (i = 0; i < reserved_bot; ++i)
		set_bit(i, bitmap->table);

		return 0;
		}

		void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap)
		{
		kfree(bitmap->table);
		}

		void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size,
		struct hns_roce_buf *buf)
		{
		int i;
		struct device *dev = &hr_dev->pdev->dev;
		u32 bits_per_long = BITS_PER_LONG;

		if (buf->nbufs == 1) {
		dma_free_coherent(dev, size, buf->direct.buf, buf->direct.map);
		} else {
		if (bits_per_long == 64)
		vunmap(buf->direct.buf);

		for (i = 0; i < buf->nbufs; ++i)
		if (buf->page_list[i].buf)
		dma_free_coherent(&hr_dev->pdev->dev, PAGE_SIZE,
		buf->page_list[i].buf,
		buf->page_list[i].map);
		kfree(buf->page_list);
		}
		}

		int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
		struct hns_roce_buf *buf)
		{
		int i = 0;
		dma_addr_t t;
		struct page **pages;
		struct device *dev = &hr_dev->pdev->dev;
		u32 bits_per_long = BITS_PER_LONG;

		/* SQ/RQ buf lease than one page, SQ + RQ = 8K */
		if (size <= max_direct) {
		buf->nbufs = 1;
		/* Npages calculated by page_size */
		buf->npages = 1 << get_order(size);
		buf->page_shift = PAGE_SHIFT;
		/* MTT PA must be recorded in 4k alignment, t is 4k aligned */
		buf->direct.buf = dma_alloc_coherent(dev, size, &t, GFP_KERNEL);
		if (!buf->direct.buf)
		return -ENOMEM;

		buf->direct.map = t;

		while (t & ((1 << buf->page_shift) - 1)) {
		--buf->page_shift;
		buf->npages *= 2;
		}

		memset(buf->direct.buf, 0, size);
		} else {
		buf->nbufs = (size + PAGE_SIZE - 1) / PAGE_SIZE;
		buf->npages = buf->nbufs;
		buf->page_shift = PAGE_SHIFT;
		buf->page_list = kcalloc(buf->nbufs, sizeof(*buf->page_list),
		GFP_KERNEL);

		if (!buf->page_list)
		return -ENOMEM;

		for (i = 0; i < buf->nbufs; ++i) {
		buf->page_list[i].buf = dma_alloc_coherent(dev,
		PAGE_SIZE, &t,
		GFP_KERNEL);

		if (!buf->page_list[i].buf)
		goto err_free;

		buf->page_list[i].map = t;
		memset(buf->page_list[i].buf, 0, PAGE_SIZE);
		}
		if (bits_per_long == 64) {
		pages = kmalloc_array(buf->nbufs, sizeof(*pages),
		GFP_KERNEL);
		if (!pages)
		goto err_free;

		for (i = 0; i < buf->nbufs; ++i)
		pages[i] = virt_to_page(buf->page_list[i].buf);

		buf->direct.buf = vmap(pages, buf->nbufs, VM_MAP,
		PAGE_KERNEL);
		kfree(pages);
		if (!buf->direct.buf)
		goto err_free;
		}
		}

		return 0;

		err_free:
		hns_roce_buf_free(hr_dev, size, buf);
		return -ENOMEM;
		}

		void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev)
		{
		hns_roce_cleanup_qp_table(hr_dev);
		hns_roce_cleanup_cq_table(hr_dev);
		hns_roce_cleanup_mr_table(hr_dev);
		hns_roce_cleanup_pd_table(hr_dev);
		hns_roce_cleanup_uar_table(hr_dev);
		}

drivers/infiniband/hw/hns/hns_roce_cmd.c

0 → 100644

+368 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2016 Hisilicon Limited.
		*
		* This software is available to you under a choice of one of two
		* licenses. You may choose to be licensed under the terms of the GNU
		* General Public License (GPL) Version 2, available from the file
		* COPYING in the main directory of this source tree, or the
		* OpenIB.org BSD license below:
		*
		* Redistribution and use in source and binary forms, with or
		* without modification, are permitted provided that the following
		* conditions are met:
		*
		* - Redistributions of source code must retain the above
		* copyright notice, this list of conditions and the following
		* disclaimer.
		*
		* - Redistributions in binary form must reproduce the above
		* copyright notice, this list of conditions and the following
		* disclaimer in the documentation and/or other materials
		* provided with the distribution.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
		* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
		* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
		* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
		* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
		* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
		* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
		* SOFTWARE.
		*/

		#include <linux/dmapool.h>
		#include <linux/platform_device.h>
		#include "hns_roce_common.h"
		#include "hns_roce_device.h"
		#include "hns_roce_cmd.h"

		#define CMD_POLL_TOKEN 0xffff
		#define CMD_MAX_NUM 32
		#define STATUS_MASK 0xff
		#define CMD_TOKEN_MASK 0x1f
		#define GO_BIT_TIMEOUT_MSECS 10000

		enum {
		HCR_TOKEN_OFFSET = 0x14,
		HCR_STATUS_OFFSET = 0x18,
		HCR_GO_BIT = 15,
		};

		static int cmd_pending(struct hns_roce_dev *hr_dev)
		{
		u32 status = readl(hr_dev->cmd.hcr + HCR_TOKEN_OFFSET);

		return (!!(status & (1 << HCR_GO_BIT)));
		}

		/* this function should be serialized with "hcr_mutex" */
		static int __hns_roce_cmd_mbox_post_hw(struct hns_roce_dev *hr_dev,
		u64 in_param, u64 out_param,
		u32 in_modifier, u8 op_modifier, u16 op,
		u16 token, int event)
		{
		struct hns_roce_cmdq *cmd = &hr_dev->cmd;
		struct device *dev = &hr_dev->pdev->dev;
		u32 __iomem hcr = (u32 )cmd->hcr;
		int ret = -EAGAIN;
		unsigned long end;
		u32 val = 0;

		end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
		while (cmd_pending(hr_dev)) {
		if (time_after(jiffies, end)) {
		dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
		(int)end);
		goto out;
		}
		cond_resched();
		}

		roce_set_field(val, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
		op);
		roce_set_field(val, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
		ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
		roce_set_bit(val, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
		roce_set_bit(val, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
		roce_set_field(val, ROCEE_MB6_ROCEE_MB_TOKEN_M,
		ROCEE_MB6_ROCEE_MB_TOKEN_S, token);

		__raw_writeq(cpu_to_le64(in_param), hcr + 0);
		__raw_writeq(cpu_to_le64(out_param), hcr + 2);
		__raw_writel(cpu_to_le32(in_modifier), hcr + 4);
		/* Memory barrier */
		wmb();

		__raw_writel(cpu_to_le32(val), hcr + 5);

		mmiowb();
		ret = 0;

		out:
		return ret;
		}

		static int hns_roce_cmd_mbox_post_hw(struct hns_roce_dev *hr_dev, u64 in_param,
		u64 out_param, u32 in_modifier,
		u8 op_modifier, u16 op, u16 token,
		int event)
		{
		struct hns_roce_cmdq *cmd = &hr_dev->cmd;
		int ret = -EAGAIN;

		mutex_lock(&cmd->hcr_mutex);
		ret = __hns_roce_cmd_mbox_post_hw(hr_dev, in_param, out_param,
		in_modifier, op_modifier, op, token,
		event);
		mutex_unlock(&cmd->hcr_mutex);

		return ret;
		}

		/* this should be called with "poll_sem" */
		static int __hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev, u64 in_param,
		u64 out_param, unsigned long in_modifier,
		u8 op_modifier, u16 op,
		unsigned long timeout)
		{
		struct device *dev = &hr_dev->pdev->dev;
		u8 __iomem *hcr = hr_dev->cmd.hcr;
		unsigned long end = 0;
		u32 status = 0;
		int ret;

		ret = hns_roce_cmd_mbox_post_hw(hr_dev, in_param, out_param,
		in_modifier, op_modifier, op,
		CMD_POLL_TOKEN, 0);
		if (ret) {
		dev_err(dev, "[cmd_poll]hns_roce_cmd_mbox_post_hw failed\n");
		goto out;
		}

		end = msecs_to_jiffies(timeout) + jiffies;
		while (cmd_pending(hr_dev) && time_before(jiffies, end))
		cond_resched();

		if (cmd_pending(hr_dev)) {
		dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
		ret = -ETIMEDOUT;
		goto out;
		}

		status = le32_to_cpu((__force __be32)
		__raw_readl(hcr + HCR_STATUS_OFFSET));
		if ((status & STATUS_MASK) != 0x1) {
		dev_err(dev, "mailbox status 0x%x!\n", status);
		ret = -EBUSY;
		goto out;
		}

		out:
		return ret;
		}

		static int hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev, u64 in_param,
		u64 out_param, unsigned long in_modifier,
		u8 op_modifier, u16 op, unsigned long timeout)
		{
		int ret;

		down(&hr_dev->cmd.poll_sem);
		ret = __hns_roce_cmd_mbox_poll(hr_dev, in_param, out_param, in_modifier,
		op_modifier, op, timeout);
		up(&hr_dev->cmd.poll_sem);

		return ret;
		}

		void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
		u64 out_param)
		{
		struct hns_roce_cmd_context
		*context = &hr_dev->cmd.context[token & hr_dev->cmd.token_mask];

		if (token != context->token)
		return;

		context->result = (status == HNS_ROCE_CMD_SUCCESS) ? 0 : (-EIO);
		context->out_param = out_param;
		complete(&context->done);
		}

		/* this should be called with "use_events" */
		static int __hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev, u64 in_param,
		u64 out_param, unsigned long in_modifier,
		u8 op_modifier, u16 op,
		unsigned long timeout)
		{
		struct hns_roce_cmdq *cmd = &hr_dev->cmd;
		struct device *dev = &hr_dev->pdev->dev;
		struct hns_roce_cmd_context *context;
		int ret = 0;

		spin_lock(&cmd->context_lock);
		WARN_ON(cmd->free_head < 0);
		context = &cmd->context[cmd->free_head];
		context->token += cmd->token_mask + 1;
		cmd->free_head = context->next;
		spin_unlock(&cmd->context_lock);

		init_completion(&context->done);

		ret = hns_roce_cmd_mbox_post_hw(hr_dev, in_param, out_param,
		in_modifier, op_modifier, op,
		context->token, 1);
		if (ret)
		goto out;

		/*
		* It is timeout when wait_for_completion_timeout return 0
		* The return value is the time limit set in advance
		* how many seconds showing
		*/
		if (!wait_for_completion_timeout(&context->done,
		msecs_to_jiffies(timeout))) {
		dev_err(dev, "[cmd]wait_for_completion_timeout timeout\n");
		ret = -EBUSY;
		goto out;
		}

		ret = context->result;
		if (ret) {
		dev_err(dev, "[cmd]event mod cmd process error!err=%d\n", ret);
		goto out;
		}

		out:
		spin_lock(&cmd->context_lock);
		context->next = cmd->free_head;
		cmd->free_head = context - cmd->context;
		spin_unlock(&cmd->context_lock);

		return ret;
		}

		static int hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev, u64 in_param,
		u64 out_param, unsigned long in_modifier,
		u8 op_modifier, u16 op, unsigned long timeout)
		{
		int ret = 0;

		down(&hr_dev->cmd.event_sem);
		ret = __hns_roce_cmd_mbox_wait(hr_dev, in_param, out_param,
		in_modifier, op_modifier, op, timeout);
		up(&hr_dev->cmd.event_sem);

		return ret;
		}

		int hns_roce_cmd_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u64 out_param,
		unsigned long in_modifier, u8 op_modifier, u16 op,
		unsigned long timeout)
		{
		if (hr_dev->cmd.use_events)
		return hns_roce_cmd_mbox_wait(hr_dev, in_param, out_param,
		in_modifier, op_modifier, op,
		timeout);
		else
		return hns_roce_cmd_mbox_poll(hr_dev, in_param, out_param,
		in_modifier, op_modifier, op,
		timeout);
		}

		int hns_roce_cmd_init(struct hns_roce_dev *hr_dev)
		{
		struct device *dev = &hr_dev->pdev->dev;

		mutex_init(&hr_dev->cmd.hcr_mutex);
		sema_init(&hr_dev->cmd.poll_sem, 1);
		hr_dev->cmd.use_events = 0;
		hr_dev->cmd.toggle = 1;
		hr_dev->cmd.max_cmds = CMD_MAX_NUM;
		hr_dev->cmd.hcr = hr_dev->reg_base + ROCEE_MB1_REG;
		hr_dev->cmd.pool = dma_pool_create("hns_roce_cmd", dev,
		HNS_ROCE_MAILBOX_SIZE,
		HNS_ROCE_MAILBOX_SIZE, 0);
		if (!hr_dev->cmd.pool)
		return -ENOMEM;

		return 0;
		}

		void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev)
		{
		dma_pool_destroy(hr_dev->cmd.pool);
		}

		int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev)
		{
		struct hns_roce_cmdq *hr_cmd = &hr_dev->cmd;
		int i;

		hr_cmd->context = kmalloc(hr_cmd->max_cmds *
		sizeof(struct hns_roce_cmd_context),
		GFP_KERNEL);
		if (!hr_cmd->context)
		return -ENOMEM;

		for (i = 0; i < hr_cmd->max_cmds; ++i) {
		hr_cmd->context[i].token = i;
		hr_cmd->context[i].next = i + 1;
		}

		hr_cmd->context[hr_cmd->max_cmds - 1].next = -1;
		hr_cmd->free_head = 0;

		sema_init(&hr_cmd->event_sem, hr_cmd->max_cmds);
		spin_lock_init(&hr_cmd->context_lock);

		hr_cmd->token_mask = CMD_TOKEN_MASK;
		hr_cmd->use_events = 1;

		down(&hr_cmd->poll_sem);

		return 0;
		}

		void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev)
		{
		struct hns_roce_cmdq *hr_cmd = &hr_dev->cmd;
		int i;

		hr_cmd->use_events = 0;

		for (i = 0; i < hr_cmd->max_cmds; ++i)
		down(&hr_cmd->event_sem);

		kfree(hr_cmd->context);
		up(&hr_cmd->poll_sem);
		}

		struct hns_roce_cmd_mailbox
		hns_roce_alloc_cmd_mailbox(struct hns_roce_dev hr_dev)
		{
		struct hns_roce_cmd_mailbox *mailbox;

		mailbox = kmalloc(sizeof(*mailbox), GFP_KERNEL);
		if (!mailbox)
		return ERR_PTR(-ENOMEM);

		mailbox->buf = dma_pool_alloc(hr_dev->cmd.pool, GFP_KERNEL,
		&mailbox->dma);
		if (!mailbox->buf) {
		kfree(mailbox);
		return ERR_PTR(-ENOMEM);
		}

		return mailbox;
		}

		void hns_roce_free_cmd_mailbox(struct hns_roce_dev *hr_dev,
		struct hns_roce_cmd_mailbox *mailbox)
		{
		if (!mailbox)
		return;

		dma_pool_free(hr_dev->cmd.pool, mailbox->buf, mailbox->dma);
		kfree(mailbox);
		}

drivers/infiniband/hw/hns/hns_roce_cmd.h

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+80 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2016 Hisilicon Limited.
		*
		* This software is available to you under a choice of one of two
		* licenses. You may choose to be licensed under the terms of the GNU
		* General Public License (GPL) Version 2, available from the file
		* COPYING in the main directory of this source tree, or the
		* OpenIB.org BSD license below:
		*
		* Redistribution and use in source and binary forms, with or
		* without modification, are permitted provided that the following
		* conditions are met:
		*
		* - Redistributions of source code must retain the above
		* copyright notice, this list of conditions and the following
		* disclaimer.
		*
		* - Redistributions in binary form must reproduce the above
		* copyright notice, this list of conditions and the following
		* disclaimer in the documentation and/or other materials
		* provided with the distribution.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
		* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
		* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
		* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
		* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
		* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
		* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
		* SOFTWARE.
		*/

		#ifndef _HNS_ROCE_CMD_H
		#define _HNS_ROCE_CMD_H

		#define HNS_ROCE_MAILBOX_SIZE 4096

		enum {
		/* TPT commands */
		HNS_ROCE_CMD_SW2HW_MPT = 0xd,
		HNS_ROCE_CMD_HW2SW_MPT = 0xf,

		/* CQ commands */
		HNS_ROCE_CMD_SW2HW_CQ = 0x16,
		HNS_ROCE_CMD_HW2SW_CQ = 0x17,

		/* QP/EE commands */
		HNS_ROCE_CMD_RST2INIT_QP = 0x19,
		HNS_ROCE_CMD_INIT2RTR_QP = 0x1a,
		HNS_ROCE_CMD_RTR2RTS_QP = 0x1b,
		HNS_ROCE_CMD_RTS2RTS_QP = 0x1c,
		HNS_ROCE_CMD_2ERR_QP = 0x1e,
		HNS_ROCE_CMD_RTS2SQD_QP = 0x1f,
		HNS_ROCE_CMD_SQD2SQD_QP = 0x38,
		HNS_ROCE_CMD_SQD2RTS_QP = 0x20,
		HNS_ROCE_CMD_2RST_QP = 0x21,
		HNS_ROCE_CMD_QUERY_QP = 0x22,
		};

		enum {
		HNS_ROCE_CMD_TIME_CLASS_A = 10000,
		HNS_ROCE_CMD_TIME_CLASS_B = 10000,
		HNS_ROCE_CMD_TIME_CLASS_C = 10000,
		};

		struct hns_roce_cmd_mailbox {
		void *buf;
		dma_addr_t dma;
		};

		int hns_roce_cmd_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u64 out_param,
		unsigned long in_modifier, u8 op_modifier, u16 op,
		unsigned long timeout);

		struct hns_roce_cmd_mailbox
		hns_roce_alloc_cmd_mailbox(struct hns_roce_dev hr_dev);
		void hns_roce_free_cmd_mailbox(struct hns_roce_dev *hr_dev,
		struct hns_roce_cmd_mailbox *mailbox);

		#endif /* _HNS_ROCE_CMD_H */

drivers/infiniband/hw/hns/hns_roce_common.h

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File added.

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