Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9a116c33 authored by blong's avatar blong
Browse files

Arm: dts: Add devfreq node for Atoll 



Add devfreq node for llcc,l3,ddr,npu and their mapping
tables for atoll.

Change-Id: Icb3562150b3d614cb4e0c7a031d11e7947870c46
Signed-off-by: default avatarBiao long <blong@codeaurora.org>
parent 29444f60

arch/arm64/boot/dts/qcom/atoll.dtsi

+297 −0
Original line number Diff line number Diff line
@@ -20,10 +20,13 @@ 
#include <dt-bindings/clock/qcom,npucc-atoll.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/clock/qcom,videocc-atoll.h>

#include <dt-bindings/clock/qcom,cpucc-sm8150.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/msm/msm-bus-ids.h>

#include <dt-bindings/soc/qcom,tcs-mbox.h>



#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))

#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}

/ {

	model = "Qualcomm Technologies, Inc. ATOLL";

	compatible = "qcom,atoll";
@@ -2456,6 +2459,300 @@ 
				<&apps_smmu 0x1030 0x1>;

		};

	};



	llcc_bw_opp_table: llcc-bw-opp-table {

		compatible = "operating-points-v2";

		BW_OPP_ENTRY( 150, 16); /*  2288 MB/s */

		BW_OPP_ENTRY( 300, 16); /*  4577 MB/s */

		BW_OPP_ENTRY( 466, 16); /*  7110 MB/s */

		BW_OPP_ENTRY( 600, 16); /*  9155 MB/s */

		BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */

		BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */

	};



	cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6300 {

		compatible = "qcom,bimc-bwmon4";

		reg = <0x90b6300 0x300>, <0x90b6200 0x200>;

		reg-names = "base", "global_base";

		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;

		qcom,mport = <0>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&cpu_cpu_llcc_bw>;

		qcom,count-unit = <0x10000>;

	};



	ddr_bw_opp_table: ddr-bw-opp-table {

		compatible = "operating-points-v2";

		BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */

		BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */

		BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */

		BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */

		BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */

		BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */

		BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */

		BW_OPP_ENTRY(2133, 4); /* 8137 MB/s */

	};



	cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 {

		compatible = "qcom,bimc-bwmon5";

		reg = <0x90cd000 0x1000>;

		reg-names = "base";

		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&cpu_llcc_ddr_bw>;

		qcom,count-unit = <0x10000>;

	};



	cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat {

		compatible = "devfreq-simple-dev";

		clock-names = "devfreq_clk";

		clocks = <&clock_cpucc L3_CLUSTER0_VOTE_CLK>;

		governor = "performance";

	};



	cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

		qcom,target-dev = <&cpu0_cpu_l3_lat>;

		qcom,cachemiss-ev = <0x17>;

		qcom,core-dev-table =

			<  768000  300000000 >,

			< 1017600  556800000 >,

			< 1248000  806400000 >,

			< 1516800  940800000 >,

			< 1804800 1401000000 >;

	};



	cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat {

		compatible = "devfreq-simple-dev";

		clock-names = "devfreq_clk";

		clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>;

		governor = "performance";

	};



	cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU6 &CPU7>;

		qcom,target-dev = <&cpu6_cpu_l3_lat>;

		qcom,cachemiss-ev = <0x17>;

		qcom,core-dev-table =

			< 1113600  556800000 >,

			< 1267200  806400000 >,

			< 1555200  940800000 >,

			< 1708800 1209600000 >,

			< 1900800 1401000000 >,

			< 2400000 1459000000 >;

	};



	cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

		qcom,target-dev = <&cpu0_cpu_llcc_lat>;

		qcom,cachemiss-ev = <0x2A>;

		qcom,core-dev-table =

			< 1248000 MHZ_TO_MBPS(300, 16) >,

			< 1516800 MHZ_TO_MBPS(466, 16) >,

			< 1804800 MHZ_TO_MBPS(600, 16) >;

	};



	cpu6_cpu_llcc_lat: qcom,cpu6-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu6_cpu_llcc_latmon: qcom,cpu6-cpu-llcc-latmon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU6 &CPU7>;

		qcom,target-dev = <&cpu6_cpu_llcc_lat>;

		qcom,cachemiss-ev = <0x2A>;

		qcom,core-dev-table =

			<  825600 MHZ_TO_MBPS(300, 16) >,

			< 1113600 MHZ_TO_MBPS(466, 16) >,

			< 1267200 MHZ_TO_MBPS(600, 16) >,

			< 1708800 MHZ_TO_MBPS(806, 16) >,

			< 2400000 MHZ_TO_MBPS(933, 16) >;

	};



	cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

		qcom,target-dev = <&cpu0_llcc_ddr_lat>;

		qcom,cachemiss-ev = <0x1000>;

		qcom,core-dev-table =

			<  768000 MHZ_TO_MBPS( 300, 4) >,

			< 1017600 MHZ_TO_MBPS( 451, 4) >,

			< 1248000 MHZ_TO_MBPS( 547, 4) >,

			< 1516800 MHZ_TO_MBPS( 768, 4) >,

			< 1804800 MHZ_TO_MBPS(1017, 4) >;

	};



	cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu6_llcc_ddr_latmon: qcom,cpu6-llcc-ddr-latmon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU6 &CPU7>;

		qcom,target-dev = <&cpu6_llcc_ddr_lat>;

		qcom,cachemiss-ev = <0x1000>;

		qcom,core-dev-table =

			< 1113600 MHZ_TO_MBPS( 547, 4) >,

			< 1267200 MHZ_TO_MBPS(1017, 4) >,

			< 1708800 MHZ_TO_MBPS(1555, 4) >,

			< 2400000 MHZ_TO_MBPS(1804, 4) >;

	};



	cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu0_computemon: qcom,cpu0-computemon {

		compatible = "qcom,arm-cpu-mon";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

		qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;

		qcom,core-dev-table =

			<  768000 MHZ_TO_MBPS( 300, 4) >,

			< 1248000 MHZ_TO_MBPS( 451, 4) >,

			< 1516800 MHZ_TO_MBPS( 547, 4) >,

			< 1804800 MHZ_TO_MBPS( 768, 4) >;

	};



	cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu6_computemon: qcom,cpu6-computemon {

		compatible = "qcom,arm-cpu-mon";

		qcom,cpulist = <&CPU6 &CPU7>;

		qcom,target-dev = <&cpu6_cpu_ddr_latfloor>;

		qcom,core-dev-table =

			< 1267200 MHZ_TO_MBPS( 547, 4) >,

			< 1555200 MHZ_TO_MBPS( 768, 4) >,

			< 1708800 MHZ_TO_MBPS(1017, 4) >,

			< 1900800 MHZ_TO_MBPS(1555, 4) >,

			< 2208000 MHZ_TO_MBPS(1804, 4) >,

			< 2400000 MHZ_TO_MBPS(2133, 4) >;

	};



	suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table {

		compatible = "operating-points-v2";

		BW_OPP_ENTRY(   0, 4); /*    0 MB/s */

		BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */

		BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */

		BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */

		BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */

		BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */

		BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */

		BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */

		BW_OPP_ENTRY(2133, 4); /* 8137 MB/s */

	};



	npu_npu_ddr_bw: qcom,npu-npu-ddr-bw {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;

		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;

		status = "disabled";

	};



	npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@00060300 {

		compatible = "qcom,bimc-bwmon4";

		reg = <0x00060300 0x300>, <0x00060200 0x200>;

		reg-names = "base", "global_base";

		clocks = <&clock_gcc GCC_NPU_BWMON_DMA_CFG_AHB_CLK>,

				<&clock_gcc GCC_NPU_BWMON_AXI_CLK>;

		clock-names = "gcc_npu_bwmon_dma_cfg_ahb_clk",

					"gcc_npu_bwmon_axi_clk";

		qcom,bwmon_clks = "gcc_npu_bwmon_dma_cfg_ahb_clk",

					"gcc_npu_bwmon_axi_clk";

		interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;

		qcom,mport = <0>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&npu_npu_ddr_bw>;

		qcom,count-unit = <0x10000>;

		status = "disabled";

	};



	npudsp_npu_ddr_bw: qcom,npudsp-npu-ddr-bw {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;

		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;

		status = "disabled";

	};



	npudsp_npu_ddr_bwmon: qcom,npudsp-npu-ddr-bwmon@70200 {

		compatible = "qcom,bimc-bwmon4";

		reg = <0x00070200 0x300>, <0x00070000 0x200>;

		reg-names = "base", "global_base";

		clocks = <&clock_gcc GCC_NPU_BWMON_DSP_CFG_AHB_CLK>,

				<&clock_gcc GCC_NPU_BWMON_AXI_CLK>;

		clock-names = "gcc_npu_bwmon_dsp_cfg_ahb_clk",

					"gcc_npu_bwmon_axi_clk";

		qcom,bwmon_clks = "gcc_npu_bwmon_dsp_cfg_ahb_clk",

					"gcc_npu_bwmon_axi_clk";

		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

		qcom,mport = <0>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&npudsp_npu_ddr_bw>;

		qcom,count-unit = <0x10000>;

		status = "disabled";

	};

};



#include "atoll-gdsc.dtsi"