Merge branch 'kvm-ppc-infrastructure' into kvm-ppc-next (99212c86) · Commits · e / devices / android_kernel_xiaomi_nabu

arch/powerpc/include/asm/book3s/64/mmu-hash.h

+37 −0

Original line number	Diff line number	Diff line
		@@ -244,6 +244,43 @@ static inline int segment_shift(int ssize)
		return SID_SHIFT_1T;
		}

		/*
		* This array is indexed by the LP field of the HPTE second dword.
		* Since this field may contain some RPN bits, some entries are
		* replicated so that we get the same value irrespective of RPN.
		* The top 4 bits are the page size index (MMU_PAGE_*) for the
		* actual page size, the bottom 4 bits are the base page size.
		*/
		extern u8 hpte_page_sizes[1 << LP_BITS];

		static inline unsigned long __hpte_page_size(unsigned long h, unsigned long l,
		bool is_base_size)
		{
		unsigned int i, lp;

		if (!(h & HPTE_V_LARGE))
		return 1ul << 12;

		/* Look at the 8 bit LP value */
		lp = (l >> LP_SHIFT) & ((1 << LP_BITS) - 1);
		i = hpte_page_sizes[lp];
		if (!i)
		return 0;
		if (!is_base_size)
		i >>= 4;
		return 1ul << mmu_psize_defs[i & 0xf].shift;
		}

		static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
		{
		return __hpte_page_size(h, l, 0);
		}

		static inline unsigned long hpte_base_page_size(unsigned long h, unsigned long l)
		{
		return __hpte_page_size(h, l, 1);
		}

		/*
		* The current system page and segment sizes
		*/

arch/powerpc/include/asm/hmi.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -21,7 +21,7 @@
		#ifndef __ASM_PPC64_HMI_H__
		#define __ASM_PPC64_HMI_H__

		#ifdef CONFIG_PPC_BOOK3S_64
		#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE

		#define CORE_TB_RESYNC_REQ_BIT 63
		#define MAX_SUBCORE_PER_CORE 4

arch/powerpc/include/asm/io.h

+29 −0

Original line number	Diff line number	Diff line
		@@ -241,6 +241,35 @@ static inline void out_be64(volatile u64 __iomem *addr, u64 val)
		#endif
		#endif /* __powerpc64__ */


		/*
		* Simple Cache inhibited accessors
		* Unlike the DEF_MMIO_* macros, these don't include any h/w memory
		* barriers, callers need to manage memory barriers on their own.
		* These can only be used in hypervisor real mode.
		*/

		static inline u32 _lwzcix(unsigned long addr)
		{
		u32 ret;

		__asm__ __volatile__("lwzcix %0,0, %1"
		: "=r" (ret) : "r" (addr) : "memory");
		return ret;
		}

		static inline void _stbcix(u64 addr, u8 val)
		{
		__asm__ __volatile__("stbcix %0,0,%1"
		: : "r" (val), "r" (addr) : "memory");
		}

		static inline void _stwcix(u64 addr, u32 val)
		{
		__asm__ __volatile__("stwcix %0,0,%1"
		: : "r" (val), "r" (addr) : "memory");
		}

		/*
		* Low level IO stream instructions are defined out of line for now
		*/

arch/powerpc/include/asm/kvm_book3s_64.h

+7 −80

Original line number	Diff line number	Diff line
		@@ -20,6 +20,8 @@
		#ifndef __ASM_KVM_BOOK3S_64_H__
		#define __ASM_KVM_BOOK3S_64_H__

		#include <asm/book3s/64/mmu-hash.h>

		#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
		static inline struct kvmppc_book3s_shadow_vcpu svcpu_get(struct kvm_vcpu vcpu)
		{
		@@ -97,56 +99,20 @@ static inline void __unlock_hpte(__be64 *hpte, unsigned long hpte_v)
		hpte[0] = cpu_to_be64(hpte_v);
		}

		static inline int __hpte_actual_psize(unsigned int lp, int psize)
		{
		int i, shift;
		unsigned int mask;

		/* start from 1 ignoring MMU_PAGE_4K */
		for (i = 1; i < MMU_PAGE_COUNT; i++) {

		/* invalid penc */
		if (mmu_psize_defs[psize].penc[i] == -1)
		continue;
		/*
		* encoding bits per actual page size
		* PTE LP actual page size
		* rrrr rrrz >=8KB
		* rrrr rrzz >=16KB
		* rrrr rzzz >=32KB
		* rrrr zzzz >=64KB
		* .......
		*/
		shift = mmu_psize_defs[i].shift - LP_SHIFT;
		if (shift > LP_BITS)
		shift = LP_BITS;
		mask = (1 << shift) - 1;
		if ((lp & mask) == mmu_psize_defs[psize].penc[i])
		return i;
		}
		return -1;
		}

		static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
		unsigned long pte_index)
		{
		int b_psize = MMU_PAGE_4K, a_psize = MMU_PAGE_4K;
		int i, b_psize = MMU_PAGE_4K, a_psize = MMU_PAGE_4K;
		unsigned int penc;
		unsigned long rb = 0, va_low, sllp;
		unsigned int lp = (r >> LP_SHIFT) & ((1 << LP_BITS) - 1);

		if (v & HPTE_V_LARGE) {
		for (b_psize = 0; b_psize < MMU_PAGE_COUNT; b_psize++) {

		/* valid entries have a shift value */
		if (!mmu_psize_defs[b_psize].shift)
		continue;

		a_psize = __hpte_actual_psize(lp, b_psize);
		if (a_psize != -1)
		break;
		}
		i = hpte_page_sizes[lp];
		b_psize = i & 0xf;
		a_psize = i >> 4;
		}

		/*
		* Ignore the top 14 bits of va
		* v have top two bits covering segment size, hence move
		@@ -215,45 +181,6 @@ static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
		return rb;
		}

		static inline unsigned long __hpte_page_size(unsigned long h, unsigned long l,
		bool is_base_size)
		{

		int size, a_psize;
		/* Look at the 8 bit LP value */
		unsigned int lp = (l >> LP_SHIFT) & ((1 << LP_BITS) - 1);

		/* only handle 4k, 64k and 16M pages for now */
		if (!(h & HPTE_V_LARGE))
		return 1ul << 12;
		else {
		for (size = 0; size < MMU_PAGE_COUNT; size++) {
		/* valid entries have a shift value */
		if (!mmu_psize_defs[size].shift)
		continue;

		a_psize = __hpte_actual_psize(lp, size);
		if (a_psize != -1) {
		if (is_base_size)
		return 1ul << mmu_psize_defs[size].shift;
		return 1ul << mmu_psize_defs[a_psize].shift;
		}
		}

		}
		return 0;
		}

		static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
		{
		return __hpte_page_size(h, l, 0);
		}

		static inline unsigned long hpte_base_page_size(unsigned long h, unsigned long l)
		{
		return __hpte_page_size(h, l, 1);
		}

		static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
		{
		return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;

arch/powerpc/include/asm/mmu.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -271,6 +271,7 @@ static inline bool early_radix_enabled(void)
		#define MMU_PAGE_16G 13
		#define MMU_PAGE_64G 14

		/* N.B. we need to change the type of hpte_page_sizes if this gets to be > 16 */
		#define MMU_PAGE_COUNT 15

		#ifdef CONFIG_PPC_BOOK3S_64