Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 98a97e6f authored by Lucas Stach's avatar Lucas Stach Committed by Bjorn Helgaas
Browse files

PCI: designware: Make get_msi_addr() return phys_addr_t, not u32 



Make get_msi_addr() return phys_addr_t, not u32.  This allows the MSI
target address to be above 4GB for 64bit or PAE systems.

No functional change for the current 32bit platform users as phys_addr_t
maps to u32 for them.

[bhelgaas: changelog]
Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarPratyush Anand <pratyush.anand@gmail.com>
parent 79707374

drivers/pci/host/pci-keystone-dw.c

+1 −1
Original line number Diff line number Diff line
@@ -70,7 +70,7 @@ static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset, 
	*bit_pos = offset >> 3;

}



u32 ks_dw_pcie_get_msi_addr(struct pcie_port *pp)

phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)

{

	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);

drivers/pci/host/pci-keystone.h

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ struct keystone_pcie { 


/* Keystone DW specific MSI controller APIs/definitions */

void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset);

u32 ks_dw_pcie_get_msi_addr(struct pcie_port *pp);

phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp);



/* Keystone specific PCI controller APIs */

void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie);

drivers/pci/host/pcie-designware.h

+1 −1
Original line number Diff line number Diff line
@@ -70,7 +70,7 @@ struct pcie_host_ops { 
	void (*host_init)(struct pcie_port *pp);

	void (*msi_set_irq)(struct pcie_port *pp, int irq);

	void (*msi_clear_irq)(struct pcie_port *pp, int irq);

	u32 (*get_msi_addr)(struct pcie_port *pp);

	phys_addr_t (*get_msi_addr)(struct pcie_port *pp);

	u32 (*get_msi_data)(struct pcie_port *pp, int pos);

	void (*scan_bus)(struct pcie_port *pp);

	int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);