Loading drivers/gpu/drm/msm/dsi-staging/dsi_phy.c +44 −0 Original line number Diff line number Diff line Loading @@ -1013,6 +1013,50 @@ int dsi_phy_set_timing_params(struct msm_dsi_phy *phy, return rc; } /** * dsi_phy_conv_phy_to_logical_lane() - Convert physical to logical lane * @lane_map: logical lane * @phy_lane: physical lane * * Return: Error code on failure. Lane number on success. */ int dsi_phy_conv_phy_to_logical_lane( struct dsi_lane_map *lane_map, enum dsi_phy_data_lanes phy_lane) { int i = 0; if (phy_lane > DSI_PHYSICAL_LANE_3) return -EINVAL; for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) { if (lane_map->lane_map_v2[i] == phy_lane) break; } return i; } /** * dsi_phy_conv_logical_to_phy_lane() - Convert logical to physical lane * @lane_map: physical lane * @lane: logical lane * * Return: Error code on failure. Lane number on success. */ int dsi_phy_conv_logical_to_phy_lane( struct dsi_lane_map *lane_map, enum dsi_logical_lane lane) { int i = 0; if (lane > (DSI_LANE_MAX - 1)) return -EINVAL; for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) { if (BIT(i) == lane_map->lane_map_v2[lane]) break; } return i; } void dsi_phy_drv_register(void) { platform_driver_register(&dsi_phy_platform_driver); Loading drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h +20 −0 Original line number Diff line number Diff line Loading @@ -268,4 +268,24 @@ struct dsi_phy_hw { struct dsi_phy_hw_ops ops; }; /** * dsi_phy_conv_phy_to_logical_lane() - Convert physical to logical lane * @lane_map: logical lane * @phy_lane: physical lane * * Return: Error code on failure. Lane number on success. */ int dsi_phy_conv_phy_to_logical_lane( struct dsi_lane_map *lane_map, enum dsi_phy_data_lanes phy_lane); /** * dsi_phy_conv_logical_to_phy_lane() - Convert logical to physical lane * @lane_map: physical lane * @lane: logical lane * * Return: Error code on failure. Lane number on success. */ int dsi_phy_conv_logical_to_phy_lane( struct dsi_lane_map *lane_map, enum dsi_logical_lane lane); #endif /* _DSI_PHY_HW_H_ */ drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v3_0.c +2 −32 Original line number Diff line number Diff line /* * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -66,36 +66,6 @@ #define DSIPHY_LNX_LPRX_CTRL(n) (0x228 + (0x80 * (n))) #define DSIPHY_LNX_TX_DCTRL(n) (0x22C + (0x80 * (n))) static inline int dsi_conv_phy_to_logical_lane( struct dsi_lane_map *lane_map, enum dsi_phy_data_lanes phy_lane) { int i = 0; if (phy_lane > DSI_PHYSICAL_LANE_3) return -EINVAL; for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) { if (lane_map->lane_map_v2[i] == phy_lane) break; } return i; } static inline int dsi_conv_logical_to_phy_lane( struct dsi_lane_map *lane_map, enum dsi_logical_lane lane) { int i = 0; if (lane > (DSI_LANE_MAX - 1)) return -EINVAL; for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) { if (BIT(i) == lane_map->lane_map_v2[lane]) break; } return i; } /** * regulator_enable() - enable regulators for DSI PHY * @phy: Pointer to DSI PHY hardware object. Loading Loading @@ -131,7 +101,7 @@ static int dsi_phy_hw_v3_0_is_pll_on(struct dsi_phy_hw *phy) static void dsi_phy_hw_v3_0_config_lpcdrx(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg, bool enable) { int phy_lane_0 = dsi_conv_logical_to_phy_lane(&cfg->lane_map, int phy_lane_0 = dsi_phy_conv_logical_to_phy_lane(&cfg->lane_map, DSI_LOGICAL_LANE_0); /* * LPRX and CDRX need to enabled only for physical data lane Loading drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c +1 −31 Original line number Diff line number Diff line Loading @@ -80,36 +80,6 @@ #define DSIPHY_LNX_LPRX_CTRL(n) (0x214 + (0x80 * (n))) #define DSIPHY_LNX_TX_DCTRL(n) (0x218 + (0x80 * (n))) static inline int dsi_conv_phy_to_logical_lane( struct dsi_lane_map *lane_map, enum dsi_phy_data_lanes phy_lane) { int i = 0; if (phy_lane > DSI_PHYSICAL_LANE_3) return -EINVAL; for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) { if (lane_map->lane_map_v2[i] == phy_lane) break; } return i; } static inline int dsi_conv_logical_to_phy_lane( struct dsi_lane_map *lane_map, enum dsi_logical_lane lane) { int i = 0; if (lane > (DSI_LANE_MAX - 1)) return -EINVAL; for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) { if (BIT(i) == lane_map->lane_map_v2[lane]) break; } return i; } static int dsi_phy_hw_v4_0_is_pll_on(struct dsi_phy_hw *phy) { u32 data = 0; Loading @@ -122,7 +92,7 @@ static int dsi_phy_hw_v4_0_is_pll_on(struct dsi_phy_hw *phy) static void dsi_phy_hw_v4_0_config_lpcdrx(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg, bool enable) { int phy_lane_0 = dsi_conv_logical_to_phy_lane(&cfg->lane_map, int phy_lane_0 = dsi_phy_conv_logical_to_phy_lane(&cfg->lane_map, DSI_LOGICAL_LANE_0); /* * LPRX and CDRX need to enabled only for physical data lane Loading Loading
drivers/gpu/drm/msm/dsi-staging/dsi_phy.c +44 −0 Original line number Diff line number Diff line Loading @@ -1013,6 +1013,50 @@ int dsi_phy_set_timing_params(struct msm_dsi_phy *phy, return rc; } /** * dsi_phy_conv_phy_to_logical_lane() - Convert physical to logical lane * @lane_map: logical lane * @phy_lane: physical lane * * Return: Error code on failure. Lane number on success. */ int dsi_phy_conv_phy_to_logical_lane( struct dsi_lane_map *lane_map, enum dsi_phy_data_lanes phy_lane) { int i = 0; if (phy_lane > DSI_PHYSICAL_LANE_3) return -EINVAL; for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) { if (lane_map->lane_map_v2[i] == phy_lane) break; } return i; } /** * dsi_phy_conv_logical_to_phy_lane() - Convert logical to physical lane * @lane_map: physical lane * @lane: logical lane * * Return: Error code on failure. Lane number on success. */ int dsi_phy_conv_logical_to_phy_lane( struct dsi_lane_map *lane_map, enum dsi_logical_lane lane) { int i = 0; if (lane > (DSI_LANE_MAX - 1)) return -EINVAL; for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) { if (BIT(i) == lane_map->lane_map_v2[lane]) break; } return i; } void dsi_phy_drv_register(void) { platform_driver_register(&dsi_phy_platform_driver); Loading
drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h +20 −0 Original line number Diff line number Diff line Loading @@ -268,4 +268,24 @@ struct dsi_phy_hw { struct dsi_phy_hw_ops ops; }; /** * dsi_phy_conv_phy_to_logical_lane() - Convert physical to logical lane * @lane_map: logical lane * @phy_lane: physical lane * * Return: Error code on failure. Lane number on success. */ int dsi_phy_conv_phy_to_logical_lane( struct dsi_lane_map *lane_map, enum dsi_phy_data_lanes phy_lane); /** * dsi_phy_conv_logical_to_phy_lane() - Convert logical to physical lane * @lane_map: physical lane * @lane: logical lane * * Return: Error code on failure. Lane number on success. */ int dsi_phy_conv_logical_to_phy_lane( struct dsi_lane_map *lane_map, enum dsi_logical_lane lane); #endif /* _DSI_PHY_HW_H_ */
drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v3_0.c +2 −32 Original line number Diff line number Diff line /* * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -66,36 +66,6 @@ #define DSIPHY_LNX_LPRX_CTRL(n) (0x228 + (0x80 * (n))) #define DSIPHY_LNX_TX_DCTRL(n) (0x22C + (0x80 * (n))) static inline int dsi_conv_phy_to_logical_lane( struct dsi_lane_map *lane_map, enum dsi_phy_data_lanes phy_lane) { int i = 0; if (phy_lane > DSI_PHYSICAL_LANE_3) return -EINVAL; for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) { if (lane_map->lane_map_v2[i] == phy_lane) break; } return i; } static inline int dsi_conv_logical_to_phy_lane( struct dsi_lane_map *lane_map, enum dsi_logical_lane lane) { int i = 0; if (lane > (DSI_LANE_MAX - 1)) return -EINVAL; for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) { if (BIT(i) == lane_map->lane_map_v2[lane]) break; } return i; } /** * regulator_enable() - enable regulators for DSI PHY * @phy: Pointer to DSI PHY hardware object. Loading Loading @@ -131,7 +101,7 @@ static int dsi_phy_hw_v3_0_is_pll_on(struct dsi_phy_hw *phy) static void dsi_phy_hw_v3_0_config_lpcdrx(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg, bool enable) { int phy_lane_0 = dsi_conv_logical_to_phy_lane(&cfg->lane_map, int phy_lane_0 = dsi_phy_conv_logical_to_phy_lane(&cfg->lane_map, DSI_LOGICAL_LANE_0); /* * LPRX and CDRX need to enabled only for physical data lane Loading
drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c +1 −31 Original line number Diff line number Diff line Loading @@ -80,36 +80,6 @@ #define DSIPHY_LNX_LPRX_CTRL(n) (0x214 + (0x80 * (n))) #define DSIPHY_LNX_TX_DCTRL(n) (0x218 + (0x80 * (n))) static inline int dsi_conv_phy_to_logical_lane( struct dsi_lane_map *lane_map, enum dsi_phy_data_lanes phy_lane) { int i = 0; if (phy_lane > DSI_PHYSICAL_LANE_3) return -EINVAL; for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) { if (lane_map->lane_map_v2[i] == phy_lane) break; } return i; } static inline int dsi_conv_logical_to_phy_lane( struct dsi_lane_map *lane_map, enum dsi_logical_lane lane) { int i = 0; if (lane > (DSI_LANE_MAX - 1)) return -EINVAL; for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) { if (BIT(i) == lane_map->lane_map_v2[lane]) break; } return i; } static int dsi_phy_hw_v4_0_is_pll_on(struct dsi_phy_hw *phy) { u32 data = 0; Loading @@ -122,7 +92,7 @@ static int dsi_phy_hw_v4_0_is_pll_on(struct dsi_phy_hw *phy) static void dsi_phy_hw_v4_0_config_lpcdrx(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg, bool enable) { int phy_lane_0 = dsi_conv_logical_to_phy_lane(&cfg->lane_map, int phy_lane_0 = dsi_phy_conv_logical_to_phy_lane(&cfg->lane_map, DSI_LOGICAL_LANE_0); /* * LPRX and CDRX need to enabled only for physical data lane Loading