Loading arch/arm64/boot/dts/qcom/trinket-gpu.dtsi +7 −4 Original line number Diff line number Diff line Loading @@ -82,11 +82,13 @@ <&clock_gpucc GPU_CC_AHB_CLK>, <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, <&clock_gcc GCC_SYS_NOC_COMPUTE_SF_AXI_CLK>, <&clock_gpucc GPU_CC_CX_GMU_CLK>; <&clock_gpucc GPU_CC_CX_GMU_CLK>, <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; clock-names = "core_clk", "rbbmtimer_clk", "mem_clk", "iface_clock", "mem_iface_clk", "alt_mem_iface_clk", "gmu_clk"; "alt_mem_iface_clk", "gmu_clk", "smmu_vote"; /* Bus Scale Settings */ qcom,gpubw-dev = <&gpubw>; Loading Loading @@ -432,10 +434,11 @@ clocks = <&clock_gcc GCC_BIMC_GPU_AXI_CLK>, <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, <&clock_gcc GCC_SYS_NOC_COMPUTE_SF_AXI_CLK>; <&clock_gcc GCC_SYS_NOC_COMPUTE_SF_AXI_CLK>, <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; clock-names = "mem_clk", "mem_iface_clk", "alt_mem_iface_clk"; "alt_mem_iface_clk", "smmu_vote"; qcom,retention; qcom,hyp_secure_alloc; Loading drivers/clk/qcom/gpucc-trinket.c +14 −0 Original line number Diff line number Diff line Loading @@ -389,6 +389,19 @@ static struct clk_branch gpu_cc_ahb_clk = { }, }; static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { .halt_reg = 0x5000, .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x5000, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_regmap *gpu_cc_trinket_clocks[] = { [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, Loading @@ -405,6 +418,7 @@ static struct clk_regmap *gpu_cc_trinket_clocks[] = { [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, }; static const struct regmap_config gpu_cc_trinket_regmap_config = { Loading drivers/gpu/msm/kgsl_pwrctrl.c +3 −2 Original line number Diff line number Diff line /* Copyright (c) 2010-2018, The Linux Foundation. All rights reserved. /* Copyright (c) 2010-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -61,7 +61,8 @@ static const char * const clocks[] = { "rbcpr_clk", "iref_clk", "gmu_clk", "ahb_clk" "ahb_clk", "smmu_vote", }; static unsigned int ib_votes[KGSL_MAX_BUSLEVELS]; Loading include/dt-bindings/clock/qcom,gpucc-trinket.h +1 −0 Original line number Diff line number Diff line Loading @@ -30,5 +30,6 @@ #define GPU_CC_GX_GFX3D_CLK 12 #define GPU_CC_GX_GFX3D_CLK_SRC 13 #define GPU_CC_AHB_CLK 14 #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 15 #endif Loading
arch/arm64/boot/dts/qcom/trinket-gpu.dtsi +7 −4 Original line number Diff line number Diff line Loading @@ -82,11 +82,13 @@ <&clock_gpucc GPU_CC_AHB_CLK>, <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, <&clock_gcc GCC_SYS_NOC_COMPUTE_SF_AXI_CLK>, <&clock_gpucc GPU_CC_CX_GMU_CLK>; <&clock_gpucc GPU_CC_CX_GMU_CLK>, <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; clock-names = "core_clk", "rbbmtimer_clk", "mem_clk", "iface_clock", "mem_iface_clk", "alt_mem_iface_clk", "gmu_clk"; "alt_mem_iface_clk", "gmu_clk", "smmu_vote"; /* Bus Scale Settings */ qcom,gpubw-dev = <&gpubw>; Loading Loading @@ -432,10 +434,11 @@ clocks = <&clock_gcc GCC_BIMC_GPU_AXI_CLK>, <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, <&clock_gcc GCC_SYS_NOC_COMPUTE_SF_AXI_CLK>; <&clock_gcc GCC_SYS_NOC_COMPUTE_SF_AXI_CLK>, <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; clock-names = "mem_clk", "mem_iface_clk", "alt_mem_iface_clk"; "alt_mem_iface_clk", "smmu_vote"; qcom,retention; qcom,hyp_secure_alloc; Loading
drivers/clk/qcom/gpucc-trinket.c +14 −0 Original line number Diff line number Diff line Loading @@ -389,6 +389,19 @@ static struct clk_branch gpu_cc_ahb_clk = { }, }; static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { .halt_reg = 0x5000, .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x5000, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_regmap *gpu_cc_trinket_clocks[] = { [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, Loading @@ -405,6 +418,7 @@ static struct clk_regmap *gpu_cc_trinket_clocks[] = { [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, }; static const struct regmap_config gpu_cc_trinket_regmap_config = { Loading
drivers/gpu/msm/kgsl_pwrctrl.c +3 −2 Original line number Diff line number Diff line /* Copyright (c) 2010-2018, The Linux Foundation. All rights reserved. /* Copyright (c) 2010-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -61,7 +61,8 @@ static const char * const clocks[] = { "rbcpr_clk", "iref_clk", "gmu_clk", "ahb_clk" "ahb_clk", "smmu_vote", }; static unsigned int ib_votes[KGSL_MAX_BUSLEVELS]; Loading
include/dt-bindings/clock/qcom,gpucc-trinket.h +1 −0 Original line number Diff line number Diff line Loading @@ -30,5 +30,6 @@ #define GPU_CC_GX_GFX3D_CLK 12 #define GPU_CC_GX_GFX3D_CLK_SRC 13 #define GPU_CC_AHB_CLK 14 #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 15 #endif