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Commit 96b6bdb5 authored by Pankaj Gupta's avatar Pankaj Gupta
Browse files

msm: kgsl: Do not enable adreno core features by default 



Do not enable Limits Management, Peak Power Detection, And
SP/TP hardware controlled power collapse feature by default.
These features should be enabled by defining in gpulist of
the target.
Without this fix respective sysfs entries will show
incorrect values.

Change-Id: I78b3cd856dc5b684023bad023ad4c96fd2bdd946
Signed-off-by: default avatarPankaj Gupta <gpankaj@codeaurora.org>
parent 83b2445d

drivers/gpu/msm/adreno.c

+1 −3
Original line number Diff line number Diff line
@@ -105,9 +105,7 @@ static struct adreno_device device_3d0 = { 
	.long_ib_detect = 1,

	.input_work = __WORK_INITIALIZER(device_3d0.input_work,

		adreno_input_work),

	.pwrctrl_flag = BIT(ADRENO_SPTP_PC_CTRL) | BIT(ADRENO_PPD_CTRL) |

		BIT(ADRENO_LM_CTRL) | BIT(ADRENO_HWCG_CTRL) |

		BIT(ADRENO_THROTTLING_CTRL),

	.pwrctrl_flag = BIT(ADRENO_HWCG_CTRL) | BIT(ADRENO_THROTTLING_CTRL),

	.profile.enabled = false,

	.active_list = LIST_HEAD_INIT(device_3d0.active_list),

	.active_list_lock = __SPIN_LOCK_UNLOCKED(device_3d0.active_list_lock),

drivers/gpu/msm/adreno_a4xx.c

+11 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2013-2018,2020 The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -1545,6 +1545,15 @@ static int a4xx_send_me_init(struct adreno_device *adreno_dev, 
	return ret;

}



static void a4xx_platform_setup(struct adreno_device *adreno_dev)

{

	if (ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC))

		set_bit(ADRENO_SPTP_PC_CTRL, &adreno_dev->pwrctrl_flag);



	if (ADRENO_FEATURE(adreno_dev, ADRENO_PPD))

		set_bit(ADRENO_PPD_CTRL, &adreno_dev->pwrctrl_flag);

}



/*

 * a4xx_rb_start() - Start the ringbuffer

 * @adreno_dev: Pointer to adreno device
@@ -1789,6 +1798,7 @@ struct adreno_gpudev adreno_a4xx_gpudev = { 


	.perfcounter_init = a4xx_perfcounter_init,

	.perfcounter_close = a4xx_perfcounter_close,

	.platform_setup = a4xx_platform_setup,

	.rb_start = a4xx_rb_start,

	.init = a4xx_init,

	.microcode_read = a3xx_microcode_read,

drivers/gpu/msm/adreno_a5xx.c

+4 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -182,6 +182,9 @@ static void a5xx_platform_setup(struct adreno_device *adreno_dev) 
	adreno_dev->lm_leakage = A530_DEFAULT_LEAKAGE;

	adreno_dev->speed_bin = 0;



	if (ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC))

		set_bit(ADRENO_SPTP_PC_CTRL, &adreno_dev->pwrctrl_flag);



	/* Check efuse bits for various capabilties */

	a5xx_check_features(adreno_dev);

}

drivers/gpu/msm/adreno_a6xx.c

+3 −0
Original line number Diff line number Diff line
@@ -2951,6 +2951,9 @@ static void a6xx_platform_setup(struct adreno_device *adreno_dev) 
		gpudev->vbif_xin_halt_ctrl0_mask =

				A6XX_VBIF_XIN_HALT_CTRL0_MASK;



	if (ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC))

		set_bit(ADRENO_SPTP_PC_CTRL, &adreno_dev->pwrctrl_flag);



	/* Check efuse bits for various capabilties */

	a6xx_check_features(adreno_dev);

}

drivers/gpu/msm/kgsl_gmu.c

+3 −4
Original line number Diff line number Diff line 
/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

/* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -1461,9 +1461,8 @@ static int gmu_probe(struct kgsl_device *device, struct device_node *node) 
				"ACD probe failed: missing or invalid table\n");

	}



	/* disable LM if the feature is not enabled */

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_LM))

		clear_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag);

	if (ADRENO_FEATURE(adreno_dev, ADRENO_LM))

		set_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag);



	set_bit(GMU_ENABLED, &device->gmu_core.flags);

	device->gmu_core.dev_ops = &adreno_a6xx_gmudev;