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Commit 95f28d2e authored by José Roberto de Souza's avatar José Roberto de Souza Committed by Rodrigo Vivi
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drm/i915/psr: Do not override PSR2 sink support 



Sink can support our PSR2 requirements but userspace can request
a resolution that PSR2 hardware do not support, in this case it
was overwritten the PSR2 sink support.
Adding another flag here, this way if requested resolution changed
to a value that PSR2 hardware can handle, PSR2 can be enabled.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180328223046.16125-6-jose.souza@intel.com
parent 5e87325f

drivers/gpu/drm/i915/i915_debugfs.c

+2 −2
Original line number Diff line number Diff line
@@ -2630,7 +2630,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) 
		   yesno(work_busy(&dev_priv->psr.work.work)));



	if (HAS_DDI(dev_priv)) {

		if (dev_priv->psr.psr2_support)

		if (dev_priv->psr.psr2_enabled)

			enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;

		else

			enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
@@ -2678,7 +2678,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) 


		seq_printf(m, "Performance_Counter: %u\n", psrperf);

	}

	if (dev_priv->psr.psr2_support) {

	if (dev_priv->psr.psr2_enabled) {

		u32 psr2 = I915_READ(EDP_PSR2_STATUS);



		seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",

drivers/gpu/drm/i915/i915_drv.h

+2 −1
Original line number Diff line number Diff line
@@ -602,11 +602,12 @@ struct i915_psr { 
	bool active;

	struct delayed_work work;

	unsigned busy_frontbuffer_bits;

	bool psr2_support;

	bool sink_psr2_support;

	bool link_standby;

	bool colorimetry_support;

	bool alpm;

	bool has_hw_tracking;

	bool psr2_enabled;



	void (*enable_source)(struct intel_dp *,

			      const struct intel_crtc_state *);

drivers/gpu/drm/i915/intel_psr.c

+17 −16
Original line number Diff line number Diff line
@@ -148,11 +148,12 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) 
		 * Y-coordinate requirement panels we would need to enable

		 * GTC first.

		 */

		dev_priv->psr.psr2_support = intel_dp_get_y_coord_required(intel_dp);

		DRM_DEBUG_KMS("PSR2 %s on sink",

			      dev_priv->psr.psr2_support ? "supported" : "not supported");

		dev_priv->psr.sink_psr2_support =

				intel_dp_get_y_coord_required(intel_dp);

		DRM_DEBUG_KMS("PSR2 %s on sink", dev_priv->psr.sink_psr2_support

			      ? "supported" : "not supported");



		if (dev_priv->psr.psr2_support) {

		if (dev_priv->psr.sink_psr2_support) {

			dev_priv->psr.colorimetry_support =

				intel_dp_get_colorimetry_status(intel_dp);

			dev_priv->psr.alpm =
@@ -193,7 +194,7 @@ static void hsw_psr_setup_vsc(struct intel_dp *intel_dp, 
	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);

	struct edp_vsc_psr psr_vsc;



	if (dev_priv->psr.psr2_support) {

	if (dev_priv->psr.psr2_enabled) {

		/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */

		memset(&psr_vsc, 0, sizeof(psr_vsc));

		psr_vsc.sdp_header.HB0 = 0;
@@ -265,7 +266,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) 
	struct drm_i915_private *dev_priv = to_i915(dev);



	/* Enable ALPM at sink for psr2 */

	if (dev_priv->psr.psr2_support && dev_priv->psr.alpm)

	if (dev_priv->psr.psr2_enabled && dev_priv->psr.alpm)

		drm_dp_dpcd_writeb(&intel_dp->aux,

				DP_RECEIVER_ALPM_CONFIG,

				DP_ALPM_ENABLE);
@@ -424,7 +425,7 @@ static void hsw_psr_activate(struct intel_dp *intel_dp) 
	 */



	/* psr1 and psr2 are mutually exclusive.*/

	if (dev_priv->psr.psr2_support)

	if (dev_priv->psr.psr2_enabled)

		hsw_activate_psr2(intel_dp);

	else

		hsw_activate_psr1(intel_dp);
@@ -444,7 +445,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 
	 * dynamically during PSR enable, and extracted from sink

	 * caps during eDP detection.

	 */

	if (!dev_priv->psr.psr2_support)

	if (!dev_priv->psr.sink_psr2_support)

		return false;



	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
@@ -543,7 +544,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp) 
	struct drm_device *dev = intel_dig_port->base.base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);



	if (dev_priv->psr.psr2_support)

	if (dev_priv->psr.psr2_enabled)

		WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);

	else

		WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
@@ -570,7 +571,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp, 
	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))

		hsw_psr_setup_aux(intel_dp);



	if (dev_priv->psr.psr2_support) {

	if (dev_priv->psr.psr2_enabled) {

		u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));



		if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
@@ -629,7 +630,7 @@ void intel_psr_enable(struct intel_dp *intel_dp, 
		goto unlock;

	}



	dev_priv->psr.psr2_support = crtc_state->has_psr2;

	dev_priv->psr.psr2_enabled = crtc_state->has_psr2;

	dev_priv->psr.busy_frontbuffer_bits = 0;



	dev_priv->psr.setup_vsc(intel_dp, crtc_state);
@@ -699,7 +700,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp, 
		i915_reg_t psr_status;

		u32 psr_status_mask;



		if (dev_priv->psr.psr2_support) {

		if (dev_priv->psr.psr2_enabled) {

			psr_status = EDP_PSR2_STATUS;

			psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
@@ -723,7 +724,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp, 


		dev_priv->psr.active = false;

	} else {

		if (dev_priv->psr.psr2_support)

		if (dev_priv->psr.psr2_enabled)

			WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);

		else

			WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
@@ -783,7 +784,7 @@ static void intel_psr_work(struct work_struct *work) 
	 * and be ready for re-enable.

	 */

	if (HAS_DDI(dev_priv)) {

		if (dev_priv->psr.psr2_support) {

		if (dev_priv->psr.psr2_enabled) {

			if (intel_wait_for_register(dev_priv,

						    EDP_PSR2_STATUS,

						    EDP_PSR2_STATUS_STATE_MASK,
@@ -842,7 +843,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv) 
		return;



	if (HAS_DDI(dev_priv)) {

		if (dev_priv->psr.psr2_support) {

		if (dev_priv->psr.psr2_enabled) {

			val = I915_READ(EDP_PSR2_CTL);

			WARN_ON(!(val & EDP_PSR2_ENABLE));

			I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
@@ -1011,7 +1012,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, 


	/* By definition flush = invalidate + flush */

	if (frontbuffer_bits) {

		if (dev_priv->psr.psr2_support ||

		if (dev_priv->psr.psr2_enabled ||

		    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

			intel_psr_exit(dev_priv);

		} else {