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Unverified Commit 953de782 authored by Mark Brown's avatar Mark Brown
Browse files

Merge branch 'asoc-4.17' into asoc-4.18 to get adau17x1 changes so

further patches can be applied.
parents 3fd391fb d0f8b9c5
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+20 −6
Original line number Diff line number Diff line
@@ -502,7 +502,7 @@ static int adau17x1_hw_params(struct snd_pcm_substream *substream,
	}

	if (adau->sigmadsp) {
		ret = adau17x1_setup_firmware(adau, params_rate(params));
		ret = adau17x1_setup_firmware(component, params_rate(params));
		if (ret < 0)
			return ret;
	}
@@ -835,26 +835,40 @@ bool adau17x1_volatile_register(struct device *dev, unsigned int reg)
}
EXPORT_SYMBOL_GPL(adau17x1_volatile_register);

int adau17x1_setup_firmware(struct adau *adau, unsigned int rate)
int adau17x1_setup_firmware(struct snd_soc_component *component,
	unsigned int rate)
{
	int ret;
	int dspsr;
	int dspsr, dsp_run;
	struct adau *adau = snd_soc_component_get_drvdata(component);
	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);

	snd_soc_dapm_mutex_lock(dapm);

	ret = regmap_read(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, &dspsr);
	if (ret)
		return ret;
		goto err;

	ret = regmap_read(adau->regmap, ADAU17X1_DSP_RUN, &dsp_run);
	if (ret)
		goto err;

	regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 1);
	regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, 0xf);
	regmap_write(adau->regmap, ADAU17X1_DSP_RUN, 0);

	ret = sigmadsp_setup(adau->sigmadsp, rate);
	if (ret) {
		regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 0);
		return ret;
		goto err;
	}
	regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dspsr);
	regmap_write(adau->regmap, ADAU17X1_DSP_RUN, dsp_run);

	return 0;
err:
	snd_soc_dapm_mutex_unlock(dapm);

	return ret;
}
EXPORT_SYMBOL_GPL(adau17x1_setup_firmware);

+2 −1
Original line number Diff line number Diff line
@@ -68,7 +68,8 @@ int adau17x1_resume(struct snd_soc_component *component);

extern const struct snd_soc_dai_ops adau17x1_dai_ops;

int adau17x1_setup_firmware(struct adau *adau, unsigned int rate);
int adau17x1_setup_firmware(struct snd_soc_component *component,
	unsigned int rate);
bool adau17x1_has_dsp(struct adau *adau);

#define ADAU17X1_CLOCK_CONTROL			0x4000
+7 −0
Original line number Diff line number Diff line
@@ -144,6 +144,13 @@ static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,

	psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;

	/* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */
	if (ratio <= 256) {
		pm = ratio;
		fp = 1;
		goto out;
	}

	/* Set the max fluctuation -- 0.1% of the max devisor */
	savesub = (psr ? 1 : 8)  * 256 * maxfp / 1000;

+11 −3
Original line number Diff line number Diff line
@@ -217,6 +217,7 @@ struct fsl_ssi_soc_data {
 * @dai_fmt: DAI configuration this device is currently used with
 * @streams: Mask of current active streams: BIT(TX) and BIT(RX)
 * @i2s_net: I2S and Network mode configurations of SCR register
 *           (this is the initial settings based on the DAI format)
 * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK
 * @use_dma: DMA is used or FIQ with stream filter
 * @use_dual_fifo: DMA with support for dual FIFO mode
@@ -829,16 +830,23 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
	}

	if (!fsl_ssi_is_ac97(ssi)) {
		/*
		 * Keep the ssi->i2s_net intact while having a local variable
		 * to override settings for special use cases. Otherwise, the
		 * ssi->i2s_net will lose the settings for regular use cases.
		 */
		u8 i2s_net = ssi->i2s_net;

		/* Normal + Network mode to send 16-bit data in 32-bit frames */
		if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16)
			ssi->i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET;
			i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET;

		/* Use Normal mode to send mono data at 1st slot of 2 slots */
		if (channels == 1)
			ssi->i2s_net = SSI_SCR_I2S_MODE_NORMAL;
			i2s_net = SSI_SCR_I2S_MODE_NORMAL;

		regmap_update_bits(regs, REG_SSI_SCR,
				   SSI_SCR_I2S_NET_MASK, ssi->i2s_net);
				   SSI_SCR_I2S_NET_MASK, i2s_net);
	}

	/* In synchronous mode, the SSI uses STCCR for capture */
+13 −9
Original line number Diff line number Diff line
@@ -72,24 +72,28 @@ config SND_SOC_INTEL_BAYTRAIL
	  for Baytrail Chromebooks but this option is now deprecated and is
	  not recommended, use SND_SST_ATOM_HIFI2_PLATFORM instead.

config SND_SST_ATOM_HIFI2_PLATFORM
	tristate
	select SND_SOC_COMPRESS

config SND_SST_ATOM_HIFI2_PLATFORM_PCI
	tristate "PCI HiFi2 (Medfield, Merrifield) Platforms"
	tristate "PCI HiFi2 (Merrifield) Platforms"
	depends on X86 && PCI
	select SND_SST_IPC_PCI
	select SND_SOC_COMPRESS
	select SND_SST_ATOM_HIFI2_PLATFORM
	help
	  If you have a Intel Medfield or Merrifield/Edison platform, then
	  If you have a Intel Merrifield/Edison platform, then
	  enable this option by saying Y or m. Distros will typically not
	  enable this option: Medfield devices are not available to
	  developers and while Merrifield/Edison can run a mainline kernel with
	  limited functionality it will require a firmware file which
	  is not in the standard firmware tree
	  enable this option: while Merrifield/Edison can run a mainline
	  kernel with limited functionality it will require a firmware file
	  which is not in the standard firmware tree

config SND_SST_ATOM_HIFI2_PLATFORM
config SND_SST_ATOM_HIFI2_PLATFORM_ACPI
	tristate "ACPI HiFi2 (Baytrail, Cherrytrail) Platforms"
	default ACPI
	depends on X86 && ACPI
	select SND_SST_IPC_ACPI
	select SND_SOC_COMPRESS
	select SND_SST_ATOM_HIFI2_PLATFORM
	select SND_SOC_ACPI_INTEL_MATCH
	select IOSF_MBI
	help
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