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Commit 940f6b48 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] Only build r4k clocksource for systems that work ok with it. 



In particular as-is it's not suited for multicore and mutiprocessors
systems where there is on guarantee that the counter are synchronized
or running from the same clock at all.  This broke Sibyte and probably
others since the "[MIPS] Handle R4000/R4400 mfc0 from count register."
commit.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 5aa85c9f

arch/mips/Kconfig

+24 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ config MACH_ALCHEMY 
config BASLER_EXCITE

	bool "Basler eXcite smart camera"

	select CEVT_R4K

	select CSRC_R4K

	select DMA_COHERENT

	select HW_HAS_PCI

	select IRQ_CPU
@@ -49,6 +50,7 @@ config BASLER_EXCITE_PROTOTYPE 
config BCM47XX

	bool "BCM47XX based boards"

	select CEVT_R4K

	select CSRC_R4K

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select IRQ_CPU
@@ -66,6 +68,7 @@ config BCM47XX 
config MIPS_COBALT

	bool "Cobalt Server"

	select CEVT_R4K

	select CSRC_R4K

	select CEVT_GT641XX

	select DMA_NONCOHERENT

	select HW_HAS_PCI
@@ -85,6 +88,7 @@ config MACH_DECSTATION 
	bool "DECstations"

	select BOOT_ELF32

	select CEVT_R4K

	select CSRC_R4K

	select DMA_NONCOHERENT

	select NO_IOPORT

	select IRQ_CPU
@@ -117,6 +121,7 @@ config MACH_JAZZ 
	select ARC32

	select ARCH_MAY_HAVE_PC_FDC

	select CEVT_R4K

	select CSRC_R4K

	select GENERIC_ISA_DMA

	select IRQ_CPU

	select I8253
@@ -137,6 +142,7 @@ config MACH_JAZZ 
config LASAT

	bool "LASAT Networks platforms"

	select CEVT_R4K

	select CSRC_R4K

	select DMA_NONCOHERENT

	select SYS_HAS_EARLY_PRINTK

	select HW_HAS_PCI
@@ -154,6 +160,7 @@ config LEMOTE_FULONG 
	bool "Lemote Fulong mini-PC"

	select ARCH_SPARSEMEM_ENABLE

	select CEVT_R4K

	select CSRC_R4K

	select SYS_HAS_CPU_LOONGSON2

	select DMA_NONCOHERENT

	select BOOT_ELF32
@@ -179,6 +186,7 @@ config MIPS_ATLAS 
	bool "MIPS Atlas board"

	select BOOT_ELF32

	select CEVT_R4K

	select CSRC_R4K

	select DMA_NONCOHERENT

	select SYS_HAS_EARLY_PRINTK

	select IRQ_CPU
@@ -210,6 +218,7 @@ config MIPS_MALTA 
	select ARCH_MAY_HAVE_PC_FDC

	select BOOT_ELF32

	select CEVT_R4K

	select CSRC_R4K

	select DMA_NONCOHERENT

	select GENERIC_ISA_DMA

	select IRQ_CPU
@@ -241,6 +250,7 @@ config MIPS_MALTA 
config MIPS_SEAD

	bool "MIPS SEAD board"

	select CEVT_R4K

	select CSRC_R4K

	select IRQ_CPU

	select DMA_NONCOHERENT

	select SYS_HAS_EARLY_PRINTK
@@ -260,6 +270,7 @@ config MIPS_SEAD 
config MIPS_SIM

	bool 'MIPS simulator (MIPSsim)'

	select CEVT_R4K

	select CSRC_R4K

	select DMA_NONCOHERENT

	select SYS_HAS_EARLY_PRINTK

	select IRQ_CPU
@@ -278,6 +289,7 @@ config MIPS_SIM 
config MARKEINS

	bool "NEC EMMA2RH Mark-eins"

	select CEVT_R4K

	select CSRC_R4K

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select IRQ_CPU
@@ -293,6 +305,7 @@ config MARKEINS 
config MACH_VR41XX

	bool "NEC VR4100 series based machines"

	select CEVT_R4K

	select CSRC_R4K

	select SYS_HAS_CPU_VR41XX

	select GENERIC_HARDIRQS_NO__DO_IRQ
@@ -330,6 +343,7 @@ config PMC_MSP 
config PMC_YOSEMITE

	bool "PMC-Sierra Yosemite eval board"

	select CEVT_R4K

	select CSRC_R4K

	select DMA_COHERENT

	select HW_HAS_PCI

	select IRQ_CPU
@@ -351,6 +365,7 @@ config PMC_YOSEMITE 
config QEMU

	bool "Qemu"

	select CEVT_R4K

	select CSRC_R4K

	select DMA_COHERENT

	select GENERIC_ISA_DMA

	select HAVE_STD_PC_SERIAL_PORT
@@ -382,6 +397,7 @@ config SGI_IP22 
	select ARC32

	select BOOT_ELF32

	select CEVT_R4K

	select CSRC_R4K

	select DMA_NONCOHERENT

	select HW_HAS_EISA

	select I8253
@@ -427,6 +443,7 @@ config SGI_IP32 
	select ARC32

	select BOOT_ELF32

	select CEVT_R4K

	select CSRC_R4K

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select IRQ_CPU
@@ -556,6 +573,7 @@ config SNI_RM 
	select ARCH_MAY_HAVE_PC_FDC

	select BOOT_ELF32

	select CEVT_R4K

	select CSRC_R4K

	select DMA_NONCOHERENT

	select GENERIC_ISA_DMA

	select HW_HAS_EISA
@@ -599,6 +617,7 @@ config TOSHIBA_JMR3927 
config TOSHIBA_RBTX4927

	bool "Toshiba RBTX49[23]7 board"

	select CEVT_R4K

	select CSRC_R4K

	select CEVT_TXX9

	select DMA_NONCOHERENT

	select HAS_TXX9_SERIAL
@@ -621,6 +640,7 @@ config TOSHIBA_RBTX4927 
config TOSHIBA_RBTX4938

	bool "Toshiba RBTX4938 board"

	select CEVT_R4K

	select CSRC_R4K

	select CEVT_TXX9

	select DMA_NONCOHERENT

	select HAS_TXX9_SERIAL
@@ -642,6 +662,7 @@ config TOSHIBA_RBTX4938 
config WR_PPMC

	bool "Wind River PPMC board"

	select CEVT_R4K

	select CSRC_R4K

	select IRQ_CPU

	select BOOT_ELF32

	select DMA_NONCOHERENT
@@ -752,6 +773,9 @@ config CEVT_TXX9 
config CSRC_BCM1480

	bool



config CSRC_R4K

	bool



config CSRC_SB1250

	bool

arch/mips/au1000/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -138,6 +138,7 @@ config SOC_AU1X00 
	bool

	select 64BIT_PHYS_ADDR

	select CEVT_R4K

	select CSRC_R4K

	select IRQ_CPU

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_SUPPORTS_32BIT_KERNEL

arch/mips/kernel/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o 
obj-$(CONFIG_CEVT_SB1250)	+= cevt-sb1250.o

obj-$(CONFIG_CEVT_TXX9)		+= cevt-txx9.o

obj-$(CONFIG_CSRC_BCM1480)	+= csrc-bcm1480.o

obj-$(CONFIG_CSRC_R4K)		+= csrc-r4k.o

obj-$(CONFIG_CSRC_SB1250)	+= csrc-sb1250.o



binfmt_irix-objs	:= irixelf.o irixinv.o irixioctl.o irixsig.o	\
@@ -43,6 +44,7 @@ obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o 
obj-$(CONFIG_CPU_VR41XX)	+= r4k_fpu.o r4k_switch.o



obj-$(CONFIG_SMP)		+= smp.o

obj-$(CONFIG_SMP_UP)		+= smp-up.o



obj-$(CONFIG_MIPS_MT)		+= mips-mt.o

obj-$(CONFIG_MIPS_MT_FPAFF)	+= mips-mt-fpaff.o

arch/mips/kernel/csrc-r4k.c

0 → 100644
+29 −0
Original line number Diff line number Diff line 
/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2007 by Ralf Baechle

 */



static cycle_t c0_hpt_read(void)

{

	return read_c0_count();

}



static struct clocksource clocksource_mips = {

	.name		= "MIPS",

	.read		= c0_hpt_read,

	.mask		= CLOCKSOURCE_MASK(32),

	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,

};



static void __init init_mips_clocksource(void)

{

	/* Calclate a somewhat reasonable rating value */

	clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;



	clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);



	clocksource_register(&clocksource_mips);

}

arch/mips/kernel/smp-up.c

0 → 100644
+67 −0
Original line number Diff line number Diff line 
/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2006, 07 by Ralf Baechle (ralf@linux-mips.org)

 *

 * Symmetric Uniprocessor (TM) Support

 */

#include <linux/kernel.h>

#include <linux/sched.h>



/*

 * Send inter-processor interrupt

 */

void up_send_ipi_single(int cpu, unsigned int action)

{

	panic(KERN_ERR "%s called", __func__);

}



static inline void up_send_ipi_mask(cpumask_t mask, unsigned int action)

{

	panic(KERN_ERR "%s called", __func__);

}



/*

 *  After we've done initial boot, this function is called to allow the

 *  board code to clean up state, if needed

 */

void __cpuinit up_init_secondary(void)

{

}



void __cpuinit up_smp_finish(void)

{

}



/* Hook for after all CPUs are online */

void up_cpus_done(void)

{

}



/*

 * Firmware CPU startup hook

 */

void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle)

{

}



void __init up_smp_setup(void)

{

}



void __init up_prepare_cpus(unsigned int max_cpus)

{

}



struct plat_smp_ops up_smp_ops = {

	.send_ipi_single	= up_send_ipi_single,

	.send_ipi_mask		= up_send_ipi_mask,

	.init_secondary		= up_init_secondary,

	.smp_finish		= up_smp_finish,

	.cpus_done		= up_cpus_done,

	.boot_secondary		= up_boot_secondary,

	.smp_setup		= up_smp_setup,

	.prepare_cpus		= up_prepare_cpus,

};