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Commit 939ee133 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "drivers: soc: qcom: Add bg pil driver to 4.14"

parents 53755517 31c8fd0a

Documentation/devicetree/bindings/pil/pil-blackghost.txt

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Qualcomm Technologies Inc Blackghost(BG) PIL driver:



Blackghost(BG) PIL driver provide interface to load and boot Blackghost(BG)

SOC. Blackghost(BG) SOC is an external SOC which communicate to MSM via

SPI. The PIL driver loads firmware into memory and invoke secure app via

qseecom to transfer and handshake the boot process. Once Blackghost(BG) SOC

is booted it raises ready interrupt which is handled by BG PIL driver, and

this event is informed to other MSM drivers, other remote subsystem via

notifier framework. The PIL driver also handles interrupt for the BG SOC

crash upon arrival of which it reset and initiates ramdump collection for BG

SOC.



Required properties:

- compatible:			Must be "qcom,pil-blackghost"

- qcom,firmware-name:		Base name of the firmware image.

- qcom,bg2ap-status-gpio:	GPIO used by the blackghost to indicate status to the apps.

- qcom,bg2ap-errfatal-gpio:	GPIO used by the blackghost to indicate software error to the apps.

- qcom,ap2bg-status-gpio:	GPIO used by the apps to indicate its status to blackghost.

- qcom,ap2bg-errfatal-gpio:	GPIO used by the apps to indicate blackghost about apps reset.



Example:



	qcom,blackghost {

		compatible = "qcom,pil-blackghost";

		qcom,firmware-name = "bgelf";



		/* GPIO inputs from blackghost */

		qcom,bg2ap-status-gpio = <&msm_gpio 97 0>;

		qcom,bg2ap-errfatal-gpio = <&msm_gpio 95 0>;

		/* GPIO output to blackghost */

		qcom,ap2bg-status-gpio = <&msm_gpio 17 0>;

		qcom,ap2bg-errfatal-gpio = <&msm_gpio 23 0>;

	};

arch/arm64/boot/dts/qcom/sdm429.dtsi

+162 −5
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@@ -16,6 +16,7 @@ 
#include <dt-bindings/clock/qcom,gcc-sdm429w.h>

#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/clock/mdss-12nm-pll-clk.h>

#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>



/ {

	model = "Qualcomm Technologies, Inc. SDM429";
@@ -533,6 +534,162 @@ 
		};

	};



	qcom,lpass@c000000 {

		compatible = "qcom,pil-tz-generic";

		reg = <0xc000000 0x00100>;



		vdd_cx-supply = <&pm660_s2_level>;

		qcom,proxy-reg-names = "vdd_cx";

		qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;



		clocks = <&rpmcc CXO_SMD_PIL_LPASS_CLK>,

			<&gcc GCC_CRYPTO_CLK>,

			<&gcc GCC_CRYPTO_AHB_CLK>,

			<&gcc GCC_CRYPTO_AXI_CLK>,

			<&gcc CRYPTO_CLK_SRC>;



		qcom,scm_core_clk_src-freq = <80000000>;

		clock-names = "xo", "scm_core_clk", "scm_iface_clk",

			"scm_bus_clk", "scm_core_clk_src";

		qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",

			"scm_bus_clk", "scm_core_clk_src";



		qcom,pas-id = <1>;

		qcom,mas-crypto = <&mas_crypto>;

		qcom,complete-ramdump;

		qcom,proxy-timeout-ms = <10000>;

		qcom,smem-id = <423>;

		qcom,sysmon-id = <1>;

		qcom,ssctl-instance-id = <0x14>;

		qcom,firmware-name = "adsp";



		/* GPIO inputs from lpass */

		interrupts-extended = <&intc 0 293 1>,

				<&adsp_smp2p_in 0 0>,

				<&adsp_smp2p_in 2 0>,

				<&adsp_smp2p_in 1 0>,

				<&adsp_smp2p_in 3 0>;



		interrupt-names = "qcom,wdog",

				"qcom,err-fatal",

				"qcom,proxy-unvote",

				"qcom,err-ready",

				"qcom,stop-ack";

		/* GPIO output to lpass */

		qcom,smem-states = <&adsp_smp2p_out 0>;

		qcom,smem-state-names = "qcom,force-stop";

		memory-region = <&adsp_fw_mem>;

	};



	qcom,pronto@a21b000 {

		compatible = "qcom,pil-tz-generic";

		reg = <0x0a21b000 0x3000>;



		vdd_pronto_pll-supply = <&pm660_l12>;

		qcom,proxy-reg-names = "vdd_pronto_pll";

		qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;



		clocks = <&rpmcc CXO_SMD_PIL_PRONTO_CLK>,

			<&gcc GCC_CRYPTO_CLK>,

			<&gcc GCC_CRYPTO_AHB_CLK>,

			<&gcc GCC_CRYPTO_AXI_CLK>,

			<&gcc CRYPTO_CLK_SRC>;

		clock-names = "xo", "scm_core_clk", "scm_iface_clk",

				"scm_bus_clk", "scm_core_clk_src";

		qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",

					"scm_bus_clk", "scm_core_clk_src";

		qcom,pas-id = <6>;

		qcom,mas-crypto = <&mas_crypto>;

		qcom,proxy-timeout-ms = <10000>;

		qcom,smem-id = <422>;

		qcom,sysmon-id = <6>;

		qcom,ssctl-instance-id = <0x13>;

		qcom,firmware-name = "wcnss";



		/* GPIO inputs from wcnss */

		interrupts-extended = <&intc 0 149 1>,

				<&wcnss_smp2p_in 0 0>,

				<&wcnss_smp2p_in 2 0>,

				<&wcnss_smp2p_in 1 0>,

				<&wcnss_smp2p_in 3 0>,

				<&wcnss_smp2p_in 7 0>;



		interrupt-names = "qcom,wdog",

				"qcom,err-fatal",

				"qcom,proxy-unvote",

				"qcom,err-ready",

				"qcom,stop-ack",

				"qcom,shutdown-ack";



		/* GPIO output to wcnss */

		qcom,smem-states = <&wcnss_smp2p_out 0>;

		qcom,smem-state-names = "qcom,force-stop";

		memory-region = <&wcnss_fw_mem>;

	};



	pil_modem: qcom,mss@4080000 {

		compatible = "qcom,pil-q6v55-mss";

		reg =   <0x4080000 0x100>,

			<0x0194f000 0x010>,

			<0x01950000 0x008>,

			<0x01951000 0x008>,

			<0x04020000 0x040>,

			<0x01871000 0x004>;

		reg-names = "qdsp6_base", "halt_q6", "halt_modem",

			"halt_nc", "rmb_base", "restart_reg",

			"cxip_lm_vote_clear";



		clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>,

			<&gcc GCC_MSS_CFG_AHB_CLK>,

			<&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,

			<&gcc GCC_BOOT_ROM_AHB_CLK>;

		clock-names = "xo", "iface_clk", "bus_clk", "mem_clk";

		qcom,proxy-clock-names = "xo";

		qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk";



		vdd_mss-supply = <&S6A>;

		vdd_cx-supply = <&pm660_s1_level_ao>;

		vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;

		vdd_mx-supply = <&pm660_s2_level_ao>;

		vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;

		vdd_pll-supply = <&L12A>;

		qcom,vdd_pll = <1800000>;

		vdd_mss-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;



		qcom,pas-id = <5>;

		qcom,pil-mss-memsetup;

		qcom,firmware-name = "modem";

		qcom,pil-self-auth;

		qcom,sequential-fw-load;

		qcom,override-acc-1 = <0x80800000>;

		qcom,sysmon-id = <0>;

		qcom,ssctl-instance-id = <0x12>;

		memory-region = <&modem_mem>;

		qcom,qdsp6v56-1-8-inrush-current;

		qcom,reset-clk;



		/* Inputs from mss */

		interrupts-extended = <&intc 0 24 1>,

				<&modem_smp2p_in 0 0>,

				<&modem_smp2p_in 2 0>,

				<&modem_smp2p_in 1 0>,

				<&modem_smp2p_in 3 0>,

				<&modem_smp2p_in 7 0>;



		interrupt-names = "qcom,wdog",

			"qcom,err-fatal",

			"qcom,proxy-unvote",

			"qcom,err-ready",

			"qcom,stop-ack",

			"qcom,shutdown-ack";



		/* Outputs to mss */

		qcom,smem-states = <&modem_smp2p_out 0>;

		qcom,smem-state-names = "qcom,force-stop";



		status = "ok";

	};



	rpm_bus: qcom,rpm-smd { };



	usb_otg: usb@78db000 {

drivers/soc/qcom/Kconfig

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@@ -1022,6 +1022,14 @@ config MSM_BAM_DMUX 
                communication between G-Link/bg_com_dev and BG processor over SPI.

                This handle the interrupts raised by BG and notify the G-link with

                interrupt event and event data.

config MSM_PIL_SSR_BG

	tristate "MSM Subsystem Blackghost(BG) Support"

	depends on MSM_PIL && MSM_SUBSYSTEM_RESTART

	help

	  Support for booting and shutting down Blackghost(BG) SOC which is

	  an external SOC. This driver communicates with Blackghost(BG) SOC

	  via pair of IPC GPIOs for inward and outward signals between MSM

	  and Blackghost(BG) SOC.



config QCOM_SOC_INFO

	bool "Chip information for QTI SoCs"

drivers/soc/qcom/Makefile

+1 −0
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@@ -69,6 +69,7 @@ obj-$(CONFIG_MSM_JTAGV8) += jtagv8.o jtagv8-etm.o 
obj-$(CONFIG_MSM_CDSP_LOADER) += qdsp6v2/

obj-$(CONFIG_QCOM_SMCINVOKE) += smcinvoke.o

obj-$(CONFIG_SDX_EXT_IPC) += sdx_ext_ipc.o

obj-$(CONFIG_MSM_PIL_SSR_BG) += subsys-pil-bg.o



ifdef CONFIG_MSM_SUBSYSTEM_RESTART

       obj-y += subsystem_notif.o

drivers/soc/qcom/pil_bg_intf.h

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/* Copyright (c) 2017-2018, 2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef __BG_INTF_H_

#define __BG_INTF_H_



#define MAX_APP_NAME_SIZE 100

#define RESULT_SUCCESS 0

#define RESULT_FAILURE -1



/* tzapp command list.*/

enum bg_tz_commands {

	BGPIL_RAMDUMP,

	BGPIL_IMAGE_LOAD,

	BGPIL_AUTH_MDT,

	BGPIL_DLOAD_CONT,

	BGPIL_GET_BG_VERSION,

};



/* tzapp bg request.*/

struct tzapp_bg_req {

	uint8_t tzapp_bg_cmd;

	uint8_t padding[3];

	phys_addr_t address_fw;

	size_t size_fw;

} __attribute__ ((__packed__));



/* tzapp bg response.*/

struct tzapp_bg_rsp {

	uint32_t tzapp_bg_cmd;

	uint32_t bg_info_len;

	int32_t status;

	uint32_t bg_info[100];

} __attribute__ ((__packed__));



#endif