Loading drivers/clk/qcom/debugcc-atoll.c +9 −0 Original line number Diff line number Diff line Loading @@ -212,6 +212,9 @@ static const char *const debug_mux_parent_names[] = { "gpu_cc_rbcpr_clk", "gpu_cc_sleep_clk", "measure_only_mccc_clk", "measure_only_cnoc_clk", "measure_only_ipa_2x_clk", "measure_only_snoc_clk", "npu_cc_atb_clk", "npu_cc_bto_core_clk", "npu_cc_bwmon_clk", Loading Loading @@ -613,6 +616,12 @@ static struct clk_debug_mux gcc_debug_mux = { 0x17, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, { "measure_only_mccc_clk", 0xC2, 1, MC_CC, 0xC2, 0x3FF, 0, 0xF, 0, 1, 0x62008, 0x62000, 0x62004 }, { "measure_only_cnoc_clk", 0x15, 1, GCC, 0x15, 0x3FF, 0, 0xF, 0, 1, 0x62008, 0x62000, 0x62004 }, { "measure_only_ipa_2x_clk", 0x128, 1, GCC, 0x128, 0x3FF, 0, 0xF, 0, 1, 0x62008, 0x62000, 0x62004 }, { "measure_only_snoc_clk", 0x7, 1, GCC, 0x7, 0x3FF, 0, 0xF, 0, 1, 0x62008, 0x62000, 0x62004 }, { "npu_cc_atb_clk", 0x16F, 4, NPU_CC, 0x17, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, { "npu_cc_bto_core_clk", 0x16F, 4, NPU_CC, Loading drivers/clk/qcom/gcc-atoll.c +41 −0 Original line number Diff line number Diff line Loading @@ -2356,7 +2356,48 @@ static struct clk_branch gcc_video_xo_clk = { }, }; /* Measure-only clock for ddrss_gcc_debug_clk. */ static struct clk_dummy measure_only_mccc_clk = { .rrate = 1000, .hw.init = &(struct clk_init_data){ .name = "measure_only_mccc_clk", .ops = &clk_dummy_ops, }, }; /* Measure-only clock for gcc_cfg_noc_ahb_clk. */ static struct clk_dummy measure_only_cnoc_clk = { .rrate = 1000, .hw.init = &(struct clk_init_data){ .name = "measure_only_cnoc_clk", .ops = &clk_dummy_ops, }, }; /* Measure-only clock for gcc_ipa_2x_clk. */ static struct clk_dummy measure_only_ipa_2x_clk = { .rrate = 1000, .hw.init = &(struct clk_init_data){ .name = "measure_only_ipa_2x_clk", .ops = &clk_dummy_ops, }, }; /* Measure-only clock for gcc_sys_noc_axi_clk. */ static struct clk_dummy measure_only_snoc_clk = { .rrate = 1000, .hw.init = &(struct clk_init_data){ .name = "measure_only_snoc_clk", .ops = &clk_dummy_ops, }, }; struct clk_hw *gcc_atoll_hws[] = { [MEASURE_ONLY_BIMC_CLK] = &measure_only_mccc_clk.hw, [MEASURE_ONLY_CNOC_CLK] = &measure_only_cnoc_clk.hw, [MEASURE_ONLY_IPA_2X_CLK] = &measure_only_ipa_2x_clk.hw, [MEASURE_ONLY_SNOC_CLK] = &measure_only_snoc_clk.hw, [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw, }; Loading Loading
drivers/clk/qcom/debugcc-atoll.c +9 −0 Original line number Diff line number Diff line Loading @@ -212,6 +212,9 @@ static const char *const debug_mux_parent_names[] = { "gpu_cc_rbcpr_clk", "gpu_cc_sleep_clk", "measure_only_mccc_clk", "measure_only_cnoc_clk", "measure_only_ipa_2x_clk", "measure_only_snoc_clk", "npu_cc_atb_clk", "npu_cc_bto_core_clk", "npu_cc_bwmon_clk", Loading Loading @@ -613,6 +616,12 @@ static struct clk_debug_mux gcc_debug_mux = { 0x17, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, { "measure_only_mccc_clk", 0xC2, 1, MC_CC, 0xC2, 0x3FF, 0, 0xF, 0, 1, 0x62008, 0x62000, 0x62004 }, { "measure_only_cnoc_clk", 0x15, 1, GCC, 0x15, 0x3FF, 0, 0xF, 0, 1, 0x62008, 0x62000, 0x62004 }, { "measure_only_ipa_2x_clk", 0x128, 1, GCC, 0x128, 0x3FF, 0, 0xF, 0, 1, 0x62008, 0x62000, 0x62004 }, { "measure_only_snoc_clk", 0x7, 1, GCC, 0x7, 0x3FF, 0, 0xF, 0, 1, 0x62008, 0x62000, 0x62004 }, { "npu_cc_atb_clk", 0x16F, 4, NPU_CC, 0x17, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, { "npu_cc_bto_core_clk", 0x16F, 4, NPU_CC, Loading
drivers/clk/qcom/gcc-atoll.c +41 −0 Original line number Diff line number Diff line Loading @@ -2356,7 +2356,48 @@ static struct clk_branch gcc_video_xo_clk = { }, }; /* Measure-only clock for ddrss_gcc_debug_clk. */ static struct clk_dummy measure_only_mccc_clk = { .rrate = 1000, .hw.init = &(struct clk_init_data){ .name = "measure_only_mccc_clk", .ops = &clk_dummy_ops, }, }; /* Measure-only clock for gcc_cfg_noc_ahb_clk. */ static struct clk_dummy measure_only_cnoc_clk = { .rrate = 1000, .hw.init = &(struct clk_init_data){ .name = "measure_only_cnoc_clk", .ops = &clk_dummy_ops, }, }; /* Measure-only clock for gcc_ipa_2x_clk. */ static struct clk_dummy measure_only_ipa_2x_clk = { .rrate = 1000, .hw.init = &(struct clk_init_data){ .name = "measure_only_ipa_2x_clk", .ops = &clk_dummy_ops, }, }; /* Measure-only clock for gcc_sys_noc_axi_clk. */ static struct clk_dummy measure_only_snoc_clk = { .rrate = 1000, .hw.init = &(struct clk_init_data){ .name = "measure_only_snoc_clk", .ops = &clk_dummy_ops, }, }; struct clk_hw *gcc_atoll_hws[] = { [MEASURE_ONLY_BIMC_CLK] = &measure_only_mccc_clk.hw, [MEASURE_ONLY_CNOC_CLK] = &measure_only_cnoc_clk.hw, [MEASURE_ONLY_IPA_2X_CLK] = &measure_only_ipa_2x_clk.hw, [MEASURE_ONLY_SNOC_CLK] = &measure_only_snoc_clk.hw, [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw, }; Loading