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Commit 92a8dd26 authored by Minas Harutyunyan's avatar Minas Harutyunyan Committed by Felipe Balbi
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usb: dwc2: host: Fix transaction errors in host mode 



Added missing GUSBCFG programming in host mode, which fixes
transaction errors issue on HiKey and Altera Cyclone V boards.

These field even if was programmed in device mode (in function
dwc2_hsotg_core_init_disconnected()) will be resetting to POR values
after core soft reset applied.
So, each time when switching to host mode required to set this field
to correct value.

Acked-by: default avatarJohn Youn <johnyoun@synopsys.com>
Signed-off-by: default avatarMinas Harutyunyan <hminas@synopsys.com>
Signed-off-by: default avatarGrigor Tovmasyan <tovmasya@synopsys.com>
Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
parent a82c7abd

drivers/usb/dwc2/hcd.c

+13 −1
Original line number Diff line number Diff line
@@ -2328,10 +2328,22 @@ static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 
 */

static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)

{

	u32 hcfg, hfir, otgctl;

	u32 hcfg, hfir, otgctl, usbcfg;



	dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);



	/* Set HS/FS Timeout Calibration to 7 (max available value).

	 * The number of PHY clocks that the application programs in

	 * this field is added to the high/full speed interpacket timeout

	 * duration in the core to account for any additional delays

	 * introduced by the PHY. This can be required, because the delay

	 * introduced by the PHY in generating the linestate condition

	 * can vary from one PHY to another.

	 */

	usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);

	usbcfg |= GUSBCFG_TOUTCAL(7);

	dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);



	/* Restart the Phy Clock */

	dwc2_writel(0, hsotg->regs + PCGCTL);