Merge "ARM: dts: msm: Add QUPV3 SE dt node for i2c on trinket" (924d9d3d) · Commits · e / devices / android_kernel_xiaomi_nabu

arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi

+289 −0

Original line number	Diff line number	Diff line
		@@ -22,5 +22,294 @@
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;

		/* QUPv3_0 SE mappings */
		/* SE 0 pin mappings */
		qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
		qupv3_se0_i2c_active: qupv3_se0_i2c_active {
		mux {
		pins = "gpio0", "gpio1";
		function = "qup00";
		};

		config {
		pins = "gpio0", "gpio1";
		drive-strength = <2>;
		bias-disable;
		};
		};
		qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
		mux {
		pins = "gpio0", "gpio1";
		function = "gpio";
		};

		config {
		pins = "gpio0", "gpio1";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		/* SE 1 pin mappings */
		qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
		qupv3_se1_i2c_active: qupv3_se1_i2c_active {
		mux {
		pins = "gpio4", "gpio5";
		function = "qup01";
		};

		config {
		pins = "gpio4", "gpio5";
		drive-strength = <2>;
		bias-disable;
		};
		};
		qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
		mux {
		pins = "gpio4", "gpio5";
		function = "gpio";
		};

		config {
		pins = "gpio4", "gpio5";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		/* SE 2 pin mappings */
		qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
		qupv3_se2_i2c_active: qupv3_se2_i2c_active {
		mux {
		pins = "gpio6", "gpio7";
		function = "qup02";
		};

		config {
		pins = "gpio6", "gpio7";
		drive-strength = <2>;
		bias-disable;
		};
		};
		qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
		mux {
		pins = "gpio6", "gpio7";
		function = "gpio";
		};

		config {
		pins = "gpio6", "gpio7";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		/* SE 3 pin mappings */
		qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
		qupv3_se3_i2c_active: qupv3_se3_i2c_active {
		mux {
		pins = "gpio14", "gpio15";
		function = "qup03";
		};

		config {
		pins = "gpio14", "gpio15";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
		mux {
		pins = "gpio14", "gpio15";
		function = "gpio";
		};

		config {
		pins = "gpio14", "gpio15";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		/* SE 4 pin mappings */
		qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
		qupv3_se4_i2c_active: qupv3_se4_i2c_active {
		mux {
		pins = "gpio16", "gpio17";
		function = "qup04";
		};

		config {
		pins = "gpio16", "gpio17";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
		mux {
		pins = "gpio16", "gpio17";
		function = "gpio";
		};

		config {
		pins = "gpio16", "gpio17";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		/QUPv3_1 SE mappings /
		/* SE 5 pin mappings */
		qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
		qupv3_se5_i2c_active: qupv3_se5_i2c_active {
		mux {
		pins = "gpio22", "gpio23";
		function = "qup10";
		};

		config {
		pins = "gpio22", "gpio23";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
		mux {
		pins = "gpio22", "gpio23";
		function = "gpio";
		};

		config {
		pins = "gpio22", "gpio23";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		/* SE 6 pin mappings */
		qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
		qupv3_se6_i2c_active: qupv3_se6_i2c_active {
		mux {
		pins = "gpio30", "gpio31";
		function = "qup11";
		};

		config {
		pins = "gpio30", "gpio31";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
		mux {
		pins = "gpio30", "gpio31";
		function = "gpio";
		};

		config {
		pins = "gpio30", "gpio31";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		/* SE 7 pin mappings */
		qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
		qupv3_se7_i2c_active: qupv3_se7_i2c_active {
		mux {
		pins = "gpio28", "gpio29";
		function = "qup12";
		};

		config {
		pins = "gpio28", "gpio29";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
		mux {
		pins = "gpio28", "gpio29";
		function = "gpio";
		};

		config {
		pins = "gpio28", "gpio29";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		/* SE 8 pin mappings */
		qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
		qupv3_se8_i2c_active: qupv3_se8_i2c_active {
		mux {
		pins = "gpio18", "gpio19";
		function = "qup13";
		};

		config {
		pins = "gpio18", "gpio19";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
		mux {
		pins = "gpio18", "gpio19";
		function = "gpio";
		};

		config {
		pins = "gpio18", "gpio19";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		/* SE 9 pin mappings */
		qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
		qupv3_se9_i2c_active: qupv3_se9_i2c_active {
		mux {
		pins = "gpio10", "gpio11";
		function = "qup14";
		};

		config {
		pins = "gpio10", "gpio11";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
		mux {
		pins = "gpio10", "gpio11";
		function = "gpio";
		};

		config {
		pins = "gpio10", "gpio11";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};
		};
		};

arch/arm64/boot/dts/qcom/trinket-qupv3.dtsi

0 → 100644

+260 −0

Original line number	Diff line number	Diff line
		/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <dt-bindings/msm/msm-bus-ids.h>

		&soc {
		/*
		* QUPv3 Instances
		* QUPv3_1 0 : SE 5
		* QUPv3_1 1 : SE 6
		* QUPv3_1 2 : SE 7
		* QUPv3_1 3 : SE 8
		* QUPv3_0 4 : SE 9
		* QUPv3_0 0 : SE 0
		* QUPv3_0 1 : SE 1
		* QUPv3_0 2 : SE 2
		* QUPv3_0 3 : SE 3
		* QUPv3_0 4 : SE 4
		*/

		/* QUPv3_0 Instances */
		qupv3_0: qcom,qupv3_0_geni_se@4ac0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x04ac0000 0x2000>;
		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_0>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
		qcom,iommu-s1-bypass;

		iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb {
		compatible = "qcom,qupv3-geni-se-cb";
		iommus = <&apps_smmu 0x123 0x0>;
		};
		};

		/* I2C */
		qupv3_se0_i2c: i2c@4a80000 {
		compatible = "qcom,i2c-geni";
		reg = <0x04a80000 0x4000>;
		interrupts = <GIC_SPI 327 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 0 3 64 0>,
		<&gpi_dma0 1 0 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se0_i2c_active>;
		pinctrl-1 = <&qupv3_se0_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		qupv3_se1_i2c: i2c@4a84000 {
		compatible = "qcom,i2c-geni";
		reg = <0x04a84000 0x4000>;
		interrupts = <GIC_SPI 328 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 1 3 64 0>,
		<&gpi_dma0 1 1 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se1_i2c_active>;
		pinctrl-1 = <&qupv3_se1_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		qupv3_se2_i2c: i2c@4a88000 {
		compatible = "qcom,i2c-geni";
		reg = <0x04a88000 0x4000>;
		interrupts = <GIC_SPI 329 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 2 3 64 0>,
		<&gpi_dma0 1 2 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se2_i2c_active>;
		pinctrl-1 = <&qupv3_se2_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		qupv3_se3_i2c: i2c@4a8c000 {
		compatible = "qcom,i2c-geni";
		reg = <0x04a8c000 0x4000>;
		interrupts = <GIC_SPI 330 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 3 3 64 0>,
		<&gpi_dma0 1 3 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se3_i2c_active>;
		pinctrl-1 = <&qupv3_se3_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		qupv3_se4_i2c: i2c@4a90000 {
		compatible = "qcom,i2c-geni";
		reg = <0x04a90000 0x4000>;
		interrupts = <GIC_SPI 331 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 4 3 64 0>,
		<&gpi_dma0 1 4 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se4_i2c_active>;
		pinctrl-1 = <&qupv3_se4_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		/* QUPv3_1 instances */
		qupv3_1: qcom,qupv3_1_geni_se@4cc0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x04cc0000 0x2000>;
		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_1>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,iommu-s1-bypass;
		iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb {
		compatible = "qcom,qupv3-geni-se-cb";
		iommus = <&apps_smmu 0x143 0x0>;
		};
		};

		/* I2C */
		qupv3_se5_i2c: i2c@4c80000 {
		compatible = "qcom,i2c-geni";
		reg = <0x04c80000 0x4000>;
		interrupts = <GIC_SPI 308 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 0 3 64 0>,
		<&gpi_dma0 1 0 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se5_i2c_active>;
		pinctrl-1 = <&qupv3_se5_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		qupv3_se6_i2c: i2c@4c84000 {
		compatible = "qcom,i2c-geni";
		reg = <0x04c84000 0x4000>;
		interrupts = <GIC_SPI 309 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 1 3 64 0>,
		<&gpi_dma0 1 1 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se6_i2c_active>;
		pinctrl-1 = <&qupv3_se6_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		qupv3_se7_i2c: i2c@4c88000 {
		compatible = "qcom,i2c-geni";
		reg = <0x04c88000 0x4000>;
		interrupts = <GIC_SPI 310 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 2 3 64 0>,
		<&gpi_dma0 1 2 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se7_i2c_active>;
		pinctrl-1 = <&qupv3_se7_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		qupv3_se8_i2c: i2c@4c8c000 {
		compatible = "qcom,i2c-geni";
		reg = <0x04c8c000 0x4000>;
		interrupts = <GIC_SPI 311 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 3 3 64 0>,
		<&gpi_dma0 1 3 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se8_i2c_active>;
		pinctrl-1 = <&qupv3_se8_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		qupv3_se9_i2c: i2c@4c90000 {
		compatible = "qcom,i2c-geni";
		reg = <0x04c90000 0x4000>;
		interrupts = <GIC_SPI 312 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 4 3 64 0>,
		<&gpi_dma0 1 4 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se9_i2c_active>;
		pinctrl-1 = <&qupv3_se9_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		};

arch/arm64/boot/dts/qcom/trinket.dtsi

+33 −0

Original line number	Diff line number	Diff line
		@@ -634,6 +634,38 @@
		qcom,config-reg = <0x0f1d1434>;
		};

		gpi_dma0: qcom,gpi-dma@0x04a00000 {
		#dma-cells = <5>;
		compatible = "qcom,gpi-dma";
		reg = <0x04a00000 0x60000>;
		reg-names = "gpi-top";
		interrupts = <0 335 0>, <0 336 0>, <0 337 0>, <0 338 0>,
		<0 339 0>, <0 340 0>, <0 341 0>, <0 342 0>;
		qcom,ev-factor = <2>;
		qcom,max-num-gpii = <8>;
		qcom,gpii-mask = <0x1f>;
		iommus = <&apps_smmu 0x0136 0x0>;
		qcom,smmu-cfg = <0x1>;
		qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
		status = "ok";
		};

		gpi_dma1: qcom,gpi-dma@0x04c00000 {
		#dma-cells = <5>;
		compatible = "qcom,gpi-dma";
		reg = <0x04c00000 0x60000>;
		reg-names = "gpi-top";
		interrupts = <0 314 0>, <0 315 0>, <0 316 0>, <0 317 0>,
		<0 318 0>, <0 319 0>, <0 320 0>, <0 321 0>;
		qcom,ev-factor = <2>;
		qcom,max-num-gpii = <8>;
		qcom,gpii-mask = <0x0f>;
		qcom,smmu-cfg = <0x1>;
		qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
		iommus = <&apps_smmu 0x0156 0x0>;
		status = "ok";
		};

		cpuss_dump: cpuss_dump {
		compatible = "qcom,cpuss-dump";
		qcom,l1_i_cache0 {
		@@ -1138,6 +1170,7 @@
		#include "trinket-gdsc.dtsi"
		#include "trinket-usb.dtsi"
		#include "msm-arm-smmu-trinket.dtsi"
		#include "trinket-qupv3.dtsi"

		&ufs_phy_gdsc {
		status = "ok";