Merge commit 'v3.1-rc9' into sched/core (9243a169) · Commits · e / devices / android_kernel_xiaomi_nabu

Documentation/networking/ip-sysctl.txt

+2 −2

Original line number	Diff line number	Diff line
		@@ -1042,7 +1042,7 @@ conf/interface/*:
		The functional behaviour for certain settings is different
		depending on whether local forwarding is enabled or not.

		accept_ra - BOOLEAN
		accept_ra - INTEGER
		Accept Router Advertisements; autoconfigure using them.

		Possible values are:
		@@ -1106,7 +1106,7 @@ dad_transmits - INTEGER
		The amount of Duplicate Address Detection probes to send.
		Default: 1

		forwarding - BOOLEAN
		forwarding - INTEGER
		Configure interface-specific Host/Router behaviour.

		Note: It is recommended to have the same setting on all

MAINTAINERS

+0 −1

Original line number	Diff line number	Diff line
		@@ -6374,7 +6374,6 @@ S: Supported
		F: arch/arm/mach-tegra

		TEHUTI ETHERNET DRIVER
		M: Alexander Indenbaum <baum@tehutinetworks.net>
		M: Andy Gospodarek <andy@greyhouse.net>
		L: netdev@vger.kernel.org
		S: Supported

Makefile

+1 −1

Original line number	Diff line number	Diff line
		VERSION = 3
		PATCHLEVEL = 1
		SUBLEVEL = 0
		EXTRAVERSION = -rc8
		EXTRAVERSION = -rc9
		NAME = "Divemaster Edition"

		# DOCUMENTATION

drivers/gpu/drm/radeon/atombios_dp.c

+10 −6

Original line number	Diff line number	Diff line
		@@ -115,6 +115,7 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
		u8 msg[20];
		int msg_bytes = send_bytes + 4;
		u8 ack;
		unsigned retry;

		if (send_bytes > 16)
		return -1;
		@@ -125,20 +126,20 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
		msg[3] = (msg_bytes << 4) \| (send_bytes - 1);
		memcpy(&msg[4], send, send_bytes);

		while (1) {
		for (retry = 0; retry < 4; retry++) {
		ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
		msg, msg_bytes, NULL, 0, delay, &ack);
		if (ret < 0)
		return ret;
		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
		break;
		return send_bytes;
		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
		udelay(400);
		else
		return -EIO;
		}

		return send_bytes;
		return -EIO;
		}

		static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
		@@ -149,26 +150,29 @@ static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
		int msg_bytes = 4;
		u8 ack;
		int ret;
		unsigned retry;

		msg[0] = address;
		msg[1] = address >> 8;
		msg[2] = AUX_NATIVE_READ << 4;
		msg[3] = (msg_bytes << 4) \| (recv_bytes - 1);

		while (1) {
		for (retry = 0; retry < 4; retry++) {
		ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
		msg, msg_bytes, recv, recv_bytes, delay, &ack);
		if (ret == 0)
		return -EPROTO;
		if (ret < 0)
		return ret;
		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
		return ret;
		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
		udelay(400);
		else if (ret == 0)
		return -EPROTO;
		else
		return -EIO;
		}

		return -EIO;
		}

		static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,

drivers/gpu/drm/radeon/evergreen.c

+0 −44

Original line number	Diff line number	Diff line
		@@ -1590,48 +1590,6 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
		return backend_map;
		}

		static void evergreen_program_channel_remap(struct radeon_device *rdev)
		{
		u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;

		tmp = RREG32(MC_SHARED_CHMAP);
		switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
		case 0:
		case 1:
		case 2:
		case 3:
		default:
		/* default mapping */
		mc_shared_chremap = 0x00fac688;
		break;
		}

		switch (rdev->family) {
		case CHIP_HEMLOCK:
		case CHIP_CYPRESS:
		case CHIP_BARTS:
		tcp_chan_steer_lo = 0x54763210;
		tcp_chan_steer_hi = 0x0000ba98;
		break;
		case CHIP_JUNIPER:
		case CHIP_REDWOOD:
		case CHIP_CEDAR:
		case CHIP_PALM:
		case CHIP_SUMO:
		case CHIP_SUMO2:
		case CHIP_TURKS:
		case CHIP_CAICOS:
		default:
		tcp_chan_steer_lo = 0x76543210;
		tcp_chan_steer_hi = 0x0000ba98;
		break;
		}

		WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
		WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
		WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
		}

		static void evergreen_gpu_init(struct radeon_device *rdev)
		{
		u32 cc_rb_backend_disable = 0;
		@@ -2078,8 +2036,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
		WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
		WREG32(HDP_ADDR_CONFIG, gb_addr_config);

		evergreen_program_channel_remap(rdev);

		num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
		grbm_gfx_index = INSTANCE_BROADCAST_WRITES;