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Commit 91d4e0aa authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Move ggtt fence/alignment to i915_gem_tiling.c 



Rename i915_gem_get_ggtt_size() and i915_gem_get_ggtt_alignment() to
i915_gem_fence_size() and i915_gem_fence_alignment() respectively to
better match usage. Similarly move the pair of functions into
i915_gem_tiling.c next to the fence restrictions.

Suggested-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170109161613.11881-6-chris@chris-wilson.co.uk


Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
parent cea84d16

drivers/gpu/drm/i915/i915_drv.h

+5 −5
Original line number Diff line number Diff line
@@ -3360,11 +3360,6 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, 
int i915_gem_open(struct drm_device *dev, struct drm_file *file);

void i915_gem_release(struct drm_device *dev, struct drm_file *file);



u32 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u32 size,

			   int tiling_mode, unsigned int stride);

u32 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u32 size,

				int tiling_mode, unsigned int stride);



int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,

				    enum i915_cache_level cache_level);
@@ -3531,6 +3526,11 @@ static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec 
		i915_gem_object_is_tiled(obj);

}



u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,

			unsigned int tiling, unsigned int stride);

u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,

			     unsigned int tiling, unsigned int stride);



/* i915_debugfs.c */

#ifdef CONFIG_DEBUG_FS

int i915_debugfs_register(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/i915_gem.c

+0 −69
Original line number Diff line number Diff line
@@ -2016,75 +2016,6 @@ void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv) 
	}

}



/**

 * i915_gem_get_ggtt_size - return required global GTT size for an object

 * @dev_priv: i915 device

 * @size: object size

 * @tiling_mode: tiling mode

 * @stride: tiling stride

 *

 * Return the required global GTT size for an object, taking into account

 * potential fence register mapping.

 */

u32 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv,

			   u32 size, int tiling_mode, unsigned int stride)

{

	u32 ggtt_size;



	GEM_BUG_ON(!size);



	if (tiling_mode == I915_TILING_NONE)

		return size;



	GEM_BUG_ON(!stride);



	if (INTEL_GEN(dev_priv) >= 4) {

		stride *= i915_gem_tile_height(tiling_mode);

		GEM_BUG_ON(stride & 4095);

		return roundup(size, stride);

	}



	/* Previous chips need a power-of-two fence region when tiling */

	if (IS_GEN3(dev_priv))

		ggtt_size = 1024*1024;

	else

		ggtt_size = 512*1024;



	while (ggtt_size < size)

		ggtt_size <<= 1;



	return ggtt_size;

}



/**

 * i915_gem_get_ggtt_alignment - return required global GTT alignment

 * @dev_priv: i915 device

 * @size: object size

 * @tiling_mode: tiling mode

 * @stride: tiling stride

 *

 * Return the required global GTT alignment for an object, taking into account

 * potential fence register mapping.

 */

u32 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u32 size,

				int tiling_mode, unsigned int stride)

{

	GEM_BUG_ON(!size);



	/*

	 * Minimum alignment is 4k (GTT page size), but might be greater

	 * if a fence register is needed for the object.

	 */

	if (INTEL_GEN(dev_priv) >= 4 || tiling_mode == I915_TILING_NONE)

		return 4096;



	/*

	 * Previous chips need to be aligned to the size of the smallest

	 * fence register that can contain the object.

	 */

	return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode, stride);

}



static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)

{

	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);

drivers/gpu/drm/i915/i915_gem_tiling.c

+77 −8
Original line number Diff line number Diff line
@@ -58,6 +58,75 @@ 
 * invovlement.

 */



/**

 * i915_gem_fence_size - required global GTT size for a fence

 * @i915: i915 device

 * @size: object size

 * @tiling: tiling mode

 * @stride: tiling stride

 *

 * Return the required global GTT size for a fence (view of a tiled object),

 * taking into account potential fence register mapping.

 */

u32 i915_gem_fence_size(struct drm_i915_private *i915,

			u32 size, unsigned int tiling, unsigned int stride)

{

	u32 ggtt_size;



	GEM_BUG_ON(!size);



	if (tiling == I915_TILING_NONE)

		return size;



	GEM_BUG_ON(!stride);



	if (INTEL_GEN(i915) >= 4) {

		stride *= i915_gem_tile_height(tiling);

		GEM_BUG_ON(stride & 4095);

		return roundup(size, stride);

	}



	/* Previous chips need a power-of-two fence region when tiling */

	if (IS_GEN3(i915))

		ggtt_size = 1024*1024;

	else

		ggtt_size = 512*1024;



	while (ggtt_size < size)

		ggtt_size <<= 1;



	return ggtt_size;

}



/**

 * i915_gem_fence_alignment - required global GTT alignment for a fence

 * @i915: i915 device

 * @size: object size

 * @tiling: tiling mode

 * @stride: tiling stride

 *

 * Return the required global GTT alignment for a fence (a view of a tiled

 * object), taking into account potential fence register mapping.

 */

u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,

			     unsigned int tiling, unsigned int stride)

{

	GEM_BUG_ON(!size);



	/*

	 * Minimum alignment is 4k (GTT page size), but might be greater

	 * if a fence register is needed for the object.

	 */

	if (INTEL_GEN(i915) >= 4 || tiling == I915_TILING_NONE)

		return 4096;



	/*

	 * Previous chips need to be aligned to the size of the smallest

	 * fence register that can contain the object.

	 */

	return i915_gem_fence_size(i915, size, tiling, stride);

}



/* Check pitch constriants for all chips & tiling formats */

static bool

i915_tiling_ok(struct drm_i915_private *dev_priv,
@@ -126,11 +195,11 @@ static bool i915_vma_fence_prepare(struct i915_vma *vma, 
	if (!i915_vma_is_map_and_fenceable(vma))

		return true;



	size = i915_gem_get_ggtt_size(i915, vma->size, tiling_mode, stride);

	size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);

	if (vma->node.size < size)

		return false;



	alignment = i915_gem_get_ggtt_alignment(i915, vma->size, tiling_mode, stride);

	alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);

	if (vma->node.start & (alignment - 1))

		return false;
@@ -276,10 +345,10 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, 
				if (!i915_vma_is_ggtt(vma))

					break;



				vma->fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size,

				vma->fence_size = i915_gem_fence_size(dev_priv, vma->size,

								      args->tiling_mode,

								      args->stride);

				vma->fence_alignment = i915_gem_get_ggtt_alignment(dev_priv, vma->size,

				vma->fence_alignment = i915_gem_fence_alignment(dev_priv, vma->size,

										args->tiling_mode,

										args->stride);

drivers/gpu/drm/i915/i915_vma.c

+6 −6
Original line number Diff line number Diff line
@@ -112,12 +112,12 @@ __i915_vma_create(struct drm_i915_gem_object *obj, 


	if (i915_is_ggtt(vm)) {

		GEM_BUG_ON(overflows_type(vma->size, u32));

		vma->fence_size = i915_gem_get_ggtt_size(vm->i915, vma->size,

		vma->fence_size = i915_gem_fence_size(vm->i915, vma->size,

						      i915_gem_object_get_tiling(obj),

						      i915_gem_object_get_stride(obj));

		GEM_BUG_ON(vma->fence_size & 4095);



		vma->fence_alignment = i915_gem_get_ggtt_alignment(vm->i915, vma->size,

		vma->fence_alignment = i915_gem_fence_alignment(vm->i915, vma->size,

								i915_gem_object_get_tiling(obj),

								i915_gem_object_get_stride(obj));

		GEM_BUG_ON(!is_power_of_2(vma->fence_alignment));