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Commit 912d6412 authored by Jim Bride's avatar Jim Bride Committed by Rodrigo Vivi
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drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init 



Bit 29 of SRD_CTL needs to have its value preserved according to the
B-Spec, so right before we write out the register we go ahead and read
the register and preserve the value of that bit before we write out
the configured register value.

v2: Spaces => tabs, minor name change, and commit message wording (Rodrigo)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarJim Bride <jim.bride@linux.intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1502229094-13392-1-git-send-email-jim.bride@linux.intel.com
parent ea46708f

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -3872,6 +3872,7 @@ enum { 
#define EDP_PSR_CTL				_MMIO(dev_priv->psr_mmio_base + 0)

#define   EDP_PSR_ENABLE			(1<<31)

#define   BDW_PSR_SINGLE_FRAME			(1<<30)

#define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK	(1<<29) /* SW can't modify */

#define   EDP_PSR_LINK_STANDBY			(1<<27)

#define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK	(3<<25)

#define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES	(0<<25)

drivers/gpu/drm/i915/intel_psr.c

+1 −0
Original line number Diff line number Diff line
@@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp) 
	else

		val |= EDP_PSR_TP1_TP2_SEL;



	val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;

	I915_WRITE(EDP_PSR_CTL, val);

}