Commit 90067998 authored May 22, 2018 by Florian Fainelli Committed by Greg Kroah-Hartman Jun 11, 2018

net: phy: broadcom: Fix auxiliary control register reads



[ Upstream commit 733a969a ]

We are currently doing auxiliary control register reads with the shadow
register value 0b111 (0x7) which incidentally is also the selector value
that should be present in bits [2:0]. Fix this by using the appropriate
selector mask which is defined (MII_BCM54XX_AUXCTL_SHDWSEL_MASK).

This does not have a functional impact yet because we always access the
MII_BCM54XX_AUXCTL_SHDWSEL_MISC (0x7) register in the current code.
This might change at some point though.

Fixes: 5b4e2900 ("net: phy: broadcom: add bcm54xx_auxctl_read")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent 8d80a839

drivers/net/phy/bcm-phy-lib.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -56,7 +56,7 @@ int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
		/* The register must be written to both the Shadow Register Select and
		* the Shadow Read Register Selector
		*/
		phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum \|
		phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MASK \|
		regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
		return phy_read(phydev, MII_BCM54XX_AUX_CTL);
		}