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Commit 8f65f349 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "Merge android-4.14-q.138 (4a805699) into msm-4.14"

parents b7c13866 07a1b124

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 4

PATCHLEVEL = 14

SUBLEVEL = 137

SUBLEVEL = 138

EXTRAVERSION =

NAME = Petit Gorille

arch/arm/boot/dts/logicpd-som-lv.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -115,10 +115,14 @@ 
};



&i2c2 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c2_pins>;

	clock-frequency = <400000>;

};



&i2c3 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c3_pins>;

	clock-frequency = <400000>;

};
@@ -241,6 +245,18 @@ 
			OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4)	/* sys_boot1.gpio_3 */

		>;

	};

	i2c2_pins: pinmux_i2c2_pins {

		pinctrl-single,pins = <

			OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0)	/* i2c2_scl */

			OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0)	/* i2c2_sda */

		>;

	};

	i2c3_pins: pinmux_i2c3_pins {

		pinctrl-single,pins = <

			OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)	/* i2c3_scl */

			OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)	/* i2c3_sda */

		>;

	};

};



&omap3_pmx_core2 {

arch/arm/boot/dts/logicpd-torpedo-som.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -121,10 +121,14 @@ 
};



&i2c2 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c2_pins>;

	clock-frequency = <400000>;

};



&i2c3 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c3_pins>;

	clock-frequency = <400000>;

	at24@50 {

		compatible = "atmel,24c64";
@@ -219,6 +223,18 @@ 
			OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0)        /* i2c1_sda.i2c1_sda */

		>;

	};

	i2c2_pins: pinmux_i2c2_pins {

		pinctrl-single,pins = <

			OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0)	/* i2c2_scl */

			OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0)	/* i2c2_sda */

		>;

	};

	i2c3_pins: pinmux_i2c3_pins {

		pinctrl-single,pins = <

			OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)	/* i2c3_scl */

			OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)	/* i2c3_sda */

		>;

	};

};



&uart2 {

arch/arm64/include/asm/cpufeature.h

+4 −3
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ enum ftr_type { 
	FTR_EXACT,			/* Use a predefined safe value */

	FTR_LOWER_SAFE,			/* Smaller value is safe */

	FTR_HIGHER_SAFE,		/* Bigger value is safe */

	FTR_HIGHER_OR_ZERO_SAFE,	/* Bigger value is safe, but 0 is biggest */

};



#define FTR_STRICT	true	/* SANITY check strict matching required */

arch/arm64/kernel/cpufeature.c

+6 −2
Original line number Diff line number Diff line
@@ -187,8 +187,8 @@ static const struct arm64_ftr_bits ftr_ctr[] = { 
	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1),		/* RES1 */

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1),	/* DIC */

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1),	/* IDC */

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),	/* CWG */

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 20, 4, 0),	/* ERG */

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 24, 4, 0),	/* CWG */

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 20, 4, 0),	/* ERG */

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),

	/*

	 * Linux can handle differing I-cache policies. Userspace JITs will
@@ -421,6 +421,10 @@ static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 
	case FTR_LOWER_SAFE:

		ret = new < cur ? new : cur;

		break;

	case FTR_HIGHER_OR_ZERO_SAFE:

		if (!cur || !new)

			break;

		/* Fallthrough */

	case FTR_HIGHER_SAFE:

		ret = new > cur ? new : cur;

		break;