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Commit 8f067837 authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk 



Skip compressing 1 segment at the end of the frame,
avoid a pixel count mismatch nuke event when last active
pixel and dummy pixel has same color for Odd Plane
Width / Height.

For both platforms Gemini Lake and Cannon Lake.

v2: Use function-like macro and also use mask to clean
    to make sure bit 11 is 0. (Suggested by Paulo).
v3: Add Display WA notation and also apply for GLK.
    Both Forgotten on v2.
    Using "GLK_" prefix since GLK came before CNL.
v4: Forgot to "|=" when moving directly macro to masked
    val. (Noticed by Paulo.)
v5: Rebased on top of 0a46ddd5 ("drm/i915/cnp: Wa 1181:
    Fix Backlight issue")

Cc: Imre Deak <imre.deak@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170905193013.31710-1-rodrigo.vivi@intel.com
parent f1294585

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -2940,6 +2940,9 @@ enum i915_power_well_id { 
#define ILK_DPFC_CHICKEN	_MMIO(0x43224)

#define   ILK_DPFC_DISABLE_DUMMY0 (1<<8)

#define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION	(1<<23)

#define   GLK_SKIP_SEG_EN		(1<<12)

#define   GLK_SKIP_SEG_COUNT_MASK	(3<<10)

#define   GLK_SKIP_SEG_COUNT(x)		((x)<<10)

#define ILK_FBC_RT_BASE		_MMIO(0x2128)

#define   ILK_FBC_RT_VALID	(1<<0)

#define   SNB_FBC_FRONT_BUFFER	(1<<1)

drivers/gpu/drm/i915/intel_pm.c

+13 −0
Original line number Diff line number Diff line
@@ -125,6 +125,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) 


static void glk_init_clock_gating(struct drm_i915_private *dev_priv)

{

	u32 val;

	gen9_init_clock_gating(dev_priv);



	/*
@@ -144,6 +145,11 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv) 
		I915_WRITE(CHICKEN_MISC_2, val);

	}



	/* Display WA #1133: WaFbcSkipSegments:glk */

	val = I915_READ(ILK_DPFC_CHICKEN);

	val &= ~GLK_SKIP_SEG_COUNT_MASK;

	val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);

	I915_WRITE(ILK_DPFC_CHICKEN, val);

}



static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
@@ -8275,6 +8281,7 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) 


static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)

{

	u32 val;

	cnp_init_clock_gating(dev_priv);



	/* This is not an Wa. Enable for better image quality */
@@ -8294,6 +8301,12 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv) 
		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,

			   I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |

			   SARBUNIT_CLKGATE_DIS);



	/* Display WA #1133: WaFbcSkipSegments:cnl */

	val = I915_READ(ILK_DPFC_CHICKEN);

	val &= ~GLK_SKIP_SEG_COUNT_MASK;

	val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);

	I915_WRITE(ILK_DPFC_CHICKEN, val);

}



static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)