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Commit 8edfbb8b authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: s/MI_STORE_DWORD_IMM_GEN8/MI_STORE_DWORD_IMM_GEN4/ 



MI_STORE_DWORD_IMM length has been the same ever since gen4. Rename
the define to avoid potential confusion if someone tries to use this
on pre-gen8.

Also correct the comment on MI_MEM_VIRTUAL bit. It's present on 945,g33
and 965 only.

Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Add USE_GGTT define for g4x+ too.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 7bcc3777

drivers/gpu/drm/i915/i915_reg.h

+3 −2
Original line number Original line Diff line number Diff line
@@ -293,8 +293,9 @@ 
#define   MI_SEMAPHORE_POLL		(1<<15)

#define   MI_SEMAPHORE_POLL		(1<<15)

#define   MI_SEMAPHORE_SAD_GTE_SDD	(1<<12)

#define   MI_SEMAPHORE_SAD_GTE_SDD	(1<<12)

#define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)

#define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)

#define MI_STORE_DWORD_IMM_GEN8	MI_INSTR(0x20, 2)

#define MI_STORE_DWORD_IMM_GEN4	MI_INSTR(0x20, 2)

#define   MI_MEM_VIRTUAL	(1 << 22) /* 965+ only */

#define   MI_MEM_VIRTUAL	(1 << 22) /* 945,g33,965 */

#define   MI_USE_GGTT		(1 << 22) /* g4x+ */

#define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)

#define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)

#define   MI_STORE_DWORD_INDEX_SHIFT 2

#define   MI_STORE_DWORD_INDEX_SHIFT 2

/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:

/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:

drivers/gpu/drm/i915/intel_lrc.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -1319,7 +1319,7 @@ static int gen8_emit_request(struct intel_ringbuffer *ringbuf) 
	if (ret)

	if (ret)

		return ret;

		return ret;





	cmd = MI_STORE_DWORD_IMM_GEN8;

	cmd = MI_STORE_DWORD_IMM_GEN4;

	cmd |= MI_GLOBAL_GTT;

	cmd |= MI_GLOBAL_GTT;





	intel_logical_ring_emit(ringbuf, cmd);

	intel_logical_ring_emit(ringbuf, cmd);