Loading drivers/gpu/drm/msm/sde/sde_crtc.c +29 −1 Original line number Diff line number Diff line Loading @@ -5822,7 +5822,11 @@ static int _sde_crtc_get_output_fence(struct drm_crtc *crtc, { struct sde_crtc *sde_crtc; struct sde_crtc_state *cstate; uint32_t offset; uint32_t offset, i; struct drm_connector_state *old_conn_state, *new_conn_state; struct drm_connector *conn; struct sde_connector *sde_conn = NULL; struct msm_display_info disp_info; bool is_vid = false; struct drm_encoder *encoder; Loading @@ -5836,6 +5840,29 @@ static int _sde_crtc_get_output_fence(struct drm_crtc *crtc, break; } /* * encoder_mask of drm_crtc_state will be zero until atomic_check * phase completes for first commit of dp. Hence, check for video * mode capability for current commit from new_connector_state. */ if (!state->encoder_mask) { for_each_oldnew_connector_in_state(state->state, conn, old_conn_state, new_conn_state, i) { if (!new_conn_state || new_conn_state->crtc != crtc) continue; sde_conn = to_sde_connector(new_conn_state->connector); if (sde_conn->display && sde_conn->ops.get_info) { sde_conn->ops.get_info(conn, &disp_info, sde_conn->display); is_vid |= disp_info.capabilities & MSM_DISPLAY_CAP_VID_MODE; if (is_vid) break; } } } offset = sde_crtc_get_property(cstate, CRTC_PROP_OUTPUT_FENCE_OFFSET); /* Loading @@ -5853,6 +5880,7 @@ static int _sde_crtc_get_output_fence(struct drm_crtc *crtc, * which will be incremented during the prepare commit phase */ offset++; SDE_EVT32(DRMID(crtc), is_vid, offset); return sde_fence_create(sde_crtc->output_fence, val, offset); } Loading Loading
drivers/gpu/drm/msm/sde/sde_crtc.c +29 −1 Original line number Diff line number Diff line Loading @@ -5822,7 +5822,11 @@ static int _sde_crtc_get_output_fence(struct drm_crtc *crtc, { struct sde_crtc *sde_crtc; struct sde_crtc_state *cstate; uint32_t offset; uint32_t offset, i; struct drm_connector_state *old_conn_state, *new_conn_state; struct drm_connector *conn; struct sde_connector *sde_conn = NULL; struct msm_display_info disp_info; bool is_vid = false; struct drm_encoder *encoder; Loading @@ -5836,6 +5840,29 @@ static int _sde_crtc_get_output_fence(struct drm_crtc *crtc, break; } /* * encoder_mask of drm_crtc_state will be zero until atomic_check * phase completes for first commit of dp. Hence, check for video * mode capability for current commit from new_connector_state. */ if (!state->encoder_mask) { for_each_oldnew_connector_in_state(state->state, conn, old_conn_state, new_conn_state, i) { if (!new_conn_state || new_conn_state->crtc != crtc) continue; sde_conn = to_sde_connector(new_conn_state->connector); if (sde_conn->display && sde_conn->ops.get_info) { sde_conn->ops.get_info(conn, &disp_info, sde_conn->display); is_vid |= disp_info.capabilities & MSM_DISPLAY_CAP_VID_MODE; if (is_vid) break; } } } offset = sde_crtc_get_property(cstate, CRTC_PROP_OUTPUT_FENCE_OFFSET); /* Loading @@ -5853,6 +5880,7 @@ static int _sde_crtc_get_output_fence(struct drm_crtc *crtc, * which will be incremented during the prepare commit phase */ offset++; SDE_EVT32(DRMID(crtc), is_vid, offset); return sde_fence_create(sde_crtc->output_fence, val, offset); } Loading