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Commit 8e12ce99 authored by Anson Huang's avatar Anson Huang Committed by Stephen Boyd
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clk: imx6sl: remove clks_init_on array 



Clock framework will enable those clocks registered
with CLK_IS_CRITICAL flag, so no need to have
clks_init_on array during clock initialization now.

ARM clock is busy divider type which has the
CLK_IS_CRITICAL flag set by default when registered.

IPG clock has no clock gate and its parent AHB clock
is busy divider type, so no need to add CLK_IS_CRITICAL
flag for IPG clock.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Reviewed-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 54614d12

drivers/clk/imx/clk-imx6sl.c

+0 −12
Original line number Diff line number Diff line
@@ -104,10 +104,6 @@ static struct clk_onecell_data clk_data; 
static void __iomem *ccm_base;

static void __iomem *anatop_base;



static const u32 clks_init_on[] __initconst = {

	IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT,

};



/*

 * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken

 *           during WAIT mode entry process could cause cache memory
@@ -195,7 +191,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) 
{

	struct device_node *np;

	void __iomem *base;

	int i;

	int ret;



	clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
@@ -426,13 +421,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) 
		pr_warn("%s: failed to set AHB clock rate %d!\n",

			__func__, ret);



	/*

	 * Make sure those always on clocks are enabled to maintain the correct

	 * usecount and enabling/disabling of parent PLLs.

	 */

	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)

		clk_prepare_enable(clks[clks_init_on[i]]);



	if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {

		clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);

		clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);