Merge "msm: npu: Limit maximum power level based on fuse register setting" (8dddb10e) · Commits · e / devices / android_kernel_xiaomi_nabu

arch/arm64/boot/dts/qcom/sdmmagpie-npu.dtsi

+5 −0

Original line number	Diff line number	Diff line
		@@ -75,6 +75,7 @@
		initial-pwrlevel = <4>;
		qcom,npu-pwrlevel@0 {
		reg = <0>;
		vreg = <1>;
		clk-freq = <300000000
		19200000
		100000000
		@@ -96,6 +97,7 @@
		};
		qcom,npu-pwrlevel@1 {
		reg = <1>;
		vreg = <2>;
		clk-freq = <400000000
		19200000
		150000000
		@@ -117,6 +119,7 @@
		};
		qcom,npu-pwrlevel@2 {
		reg = <2>;
		vreg = <3>;
		clk-freq = <466500000
		19200000
		200000000
		@@ -138,6 +141,7 @@
		};
		qcom,npu-pwrlevel@3 {
		reg = <3>;
		vreg = <4>;
		clk-freq = <600000000
		19200000
		300000000
		@@ -159,6 +163,7 @@
		};
		qcom,npu-pwrlevel@4 {
		reg = <4>;
		vreg = <6>;
		clk-freq = <700000000
		19200000
		400000000

arch/arm64/boot/dts/qcom/sm8150-npu.dtsi

+5 −0

Original line number	Diff line number	Diff line
		@@ -78,6 +78,7 @@
		initial-pwrlevel = <4>;
		qcom,npu-pwrlevel@0 {
		reg = <0>;
		vreg = <1>;
		clk-freq = <300000000
		19200000
		100000000
		@@ -101,6 +102,7 @@
		};
		qcom,npu-pwrlevel@1 {
		reg = <1>;
		vreg = <2>;
		clk-freq = <350000000
		19200000
		150000000
		@@ -124,6 +126,7 @@
		};
		qcom,npu-pwrlevel@2 {
		reg = <2>;
		vreg = <3>;
		clk-freq = <400000000
		19200000
		200000000
		@@ -147,6 +150,7 @@
		};
		qcom,npu-pwrlevel@3 {
		reg = <3>;
		vreg = <4>;
		clk-freq = <600000000
		19200000
		300000000
		@@ -170,6 +174,7 @@
		};
		qcom,npu-pwrlevel@4 {
		reg = <4>;
		vreg = <6>;
		clk-freq = <715000000
		19200000
		350000000

arch/arm64/boot/dts/qcom/sm8150-v2.dtsi

+6 −0

Original line number	Diff line number	Diff line
		@@ -697,6 +697,7 @@
		initial-pwrlevel = <5>;
		qcom,npu-pwrlevel@0 {
		reg = <0>;
		vreg = <1>;
		clk-freq = <300000000
		19200000
		100000000
		@@ -720,6 +721,7 @@
		};
		qcom,npu-pwrlevel@1 {
		reg = <1>;
		vreg = <2>;
		clk-freq = <400000000
		19200000
		150000000
		@@ -743,6 +745,7 @@
		};
		qcom,npu-pwrlevel@2 {
		reg = <2>;
		vreg = <3>;
		clk-freq = <487000000
		19200000
		200000000
		@@ -766,6 +769,7 @@
		};
		qcom,npu-pwrlevel@3 {
		reg = <3>;
		vreg = <4>;
		clk-freq = <652000000
		19200000
		300000000
		@@ -789,6 +793,7 @@
		};
		qcom,npu-pwrlevel@4 {
		reg = <4>;
		vreg = <6>;
		clk-freq = <811000000
		19200000
		400000000
		@@ -812,6 +817,7 @@
		};
		qcom,npu-pwrlevel@5 {
		reg = <5>;
		vreg = <7>;
		clk-freq = <908000000
		19200000
		400000000

drivers/media/platform/msm/npu/npu_common.h

+27 −3

Original line number	Diff line number	Diff line
		@@ -50,6 +50,18 @@
		#define NPU_MAX_PWRLEVELS 8
		#define NPU_MAX_STATS_BUF_SIZE 16384

		enum npu_power_level {
		NPU_PWRLEVEL_MINSVS = 0,
		NPU_PWRLEVEL_LOWSVS,
		NPU_PWRLEVEL_SVS,
		NPU_PWRLEVEL_SVS_L1,
		NPU_PWRLEVEL_NORM,
		NPU_PWRLEVEL_NORM_L1,
		NPU_PWRLEVEL_TURBO,
		NPU_PWRLEVEL_TURBO_L1,
		NPU_PWRLEVEL_OFF = 0xFFFFFFFF,
		};

		/* -------------------------------------------------------------------------
		* Data Structures
		* -------------------------------------------------------------------------
		@@ -107,9 +119,11 @@ struct npu_mbox {
		/**
		* struct npul_pwrlevel - Struct holding different pwrlevel info obtained from
		* from dtsi file
		* @pwr_level: NPU power level
		* @freq[]: NPU frequency vote in Hz
		*/
		struct npu_pwrlevel {
		uint32_t pwr_level;
		long clk_freq[NUM_MAX_CLK_NUM];
		};

		@@ -134,6 +148,10 @@ struct npu_reg {
		* @max_pwrlevel - maximum allowable powerlevel per the user
		* @min_pwrlevel - minimum allowable powerlevel per the user
		* @num_pwrlevels - number of available power levels
		* @fmax_pwrlevel - maximum power level from qfprom fmax setting
		* @uc_pwrlevel - power level from user driver setting
		* @perf_mode_override - perf mode from sysfs to override perf mode
		* settings from user driver
		* @devbw - bw device
		*/
		struct npu_pwrctrl {
		@@ -149,6 +167,8 @@ struct npu_pwrctrl {
		struct device *devbw;
		uint32_t bwmon_enabled;
		uint32_t uc_pwrlevel;
		uint32_t fmax_pwrlevel;
		uint32_t perf_mode_override;
		};

		/**
		@@ -171,6 +191,11 @@ struct npu_irq {
		int irq_type;
		};

		struct npu_io_data {
		size_t size;
		void __iomem *base;
		};

		struct npu_device {
		struct mutex dev_lock;

		@@ -181,9 +206,8 @@ struct npu_device {
		struct class *class;
		struct device *device;

		size_t reg_size;
		char __iomem *npu_base;
		uint32_t npu_phys;
		struct npu_io_data npu_io;
		struct npu_io_data qfprom_io;

		uint32_t core_clk_num;
		struct npu_clk core_clks[NUM_MAX_CLK_NUM];

drivers/media/platform/msm/npu/npu_debugfs.c

+11 −21

Original line number	Diff line number	Diff line
		@@ -169,7 +169,7 @@ static ssize_t npu_debug_reg_read(struct file *file,
		if (!debugfs->buf)
		return -ENOMEM;

		ptr = npu_dev->npu_base + debugfs->reg_off;
		ptr = npu_dev->npu_io.base + debugfs->reg_off;
		tot = 0;
		off = (int)debugfs->reg_off;

		@@ -183,7 +183,7 @@ static ssize_t npu_debug_reg_read(struct file *file,
		len = scnprintf(debugfs->buf + tot,
		debugfs->buf_len - tot, "0x%08x: %s\n",
		((int) (unsigned long) ptr) -
		((int) (unsigned long) npu_dev->npu_base),
		((int) (unsigned long) npu_dev->npu_io.base),
		dump_buf);

		ptr += ROW_BYTES;
		@@ -352,6 +352,7 @@ static ssize_t npu_debug_ctrl_write(struct file *file,
		struct npu_device *npu_dev = file->private_data;
		struct npu_debugfs_ctx *debugfs;
		int32_t rc = 0;
		uint32_t val;

		pr_debug("npu_dev %pK %pK\n", npu_dev, g_npu_dev);
		npu_dev = g_npu_dev;
		@@ -390,26 +391,15 @@ static ssize_t npu_debug_ctrl_write(struct file *file,
		pr_debug("loopback test\n");
		rc = npu_host_loopback_test(npu_dev);
		pr_debug("loopback test end: %d\n", rc);
		} else if (strcmp(buf, "0") == 0) {
		pr_info("setting power state to 0\n");
		npu_dev->pwrctrl.active_pwrlevel = 0;
		} else if (strcmp(buf, "1") == 0) {
		pr_info("setting power state to 1\n");
		npu_dev->pwrctrl.active_pwrlevel = 1;
		} else if (strcmp(buf, "2") == 0) {
		pr_info("setting power state to 2\n");
		npu_dev->pwrctrl.active_pwrlevel = 2;
		} else if (strcmp(buf, "3") == 0) {
		pr_info("setting power state to 3\n");
		npu_dev->pwrctrl.active_pwrlevel = 3;
		} else if (strcmp(buf, "4") == 0) {
		pr_info("setting power state to 4\n");
		npu_dev->pwrctrl.active_pwrlevel = 4;
		} else if (strcmp(buf, "5") == 0) {
		pr_info("setting power state to 5\n");
		npu_dev->pwrctrl.active_pwrlevel = 5;
		} else {
		pr_info("ctrl invalid value\n");
		rc = kstrtou32(buf, 10, &val);
		if (rc) {
		pr_err("Invalid input for power level settings\n");
		} else {
		val = min(val, npu_dev->pwrctrl.max_pwrlevel);
		npu_dev->pwrctrl.active_pwrlevel = val;
		pr_info("setting power state to %d\n", val);
		}
		}

		return count;