drm/msm/sde: set correct bit width in qseed op mode

Set the correct bit width when programming the qseed op mode
register via the reg dma path.  The logic was inverted
from what HW expects which lead to incorrect processing of
alpha blending use cases on VIG RECT0 pipes.

Change-Id: I67b10376407ab63e19168e80a714fdeaf18912c5
Signed-off-by: Steve Cohen <cohens@codeaurora.org>