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Commit 8bbecf1d authored by Ritesh Kumar's avatar Ritesh Kumar Committed by Gerrit - the friendly Code Review server
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drm: msm: dsi-staging: Add support to skip phy timing update 



For some panels, PHY timing parameters are not as per mipi specs.
This change adds supoort to skip phy timing update during clock
switch.

Change-Id: Ibe3d689e72dd644d5c6fd1acc8125d2a0b826bf7
Signed-off-by: default avatarRitesh Kumar <riteshk@codeaurora.org>
parent e9c93285

Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt

+2 −0
Original line number Diff line number Diff line
@@ -551,6 +551,8 @@ Optional properties: 
					is supported.

- qcom,dsi-dyn-clk-list:		An u32 array which lists all the supported dsi bit clock

					frequencies in Hz for the given panel.

- qcom,dsi-dyn-clk-skip-timing-update:	Boolean to specify whether to skip phy timing parameter

					update during dynamic clock switch.



Required properties for sub-nodes:	None

Optional properties:

drivers/gpu/drm/msm/dsi-staging/dsi_display.c

+8 −4
Original line number Diff line number Diff line
@@ -4175,6 +4175,7 @@ static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display, 
	struct dsi_dyn_clk_delay delay;

	struct link_clk_freq bkp_freq;

	bool is_cphy;

	struct dsi_dyn_clk_caps *dyn_clk_caps;



	dsi_panel_acquire_panel_lock(display->panel);
@@ -4190,11 +4191,14 @@ static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display, 
	dsi_display_mask_ctrl_error_interrupts(display, mask, true);



	/* update the phy timings based on new mode */

	dyn_clk_caps = &display->panel->dyn_clk_caps;

	if (!dyn_clk_caps->skip_phy_timing_update) {

		display_for_each_ctrl(i, display) {

			ctrl = &display->ctrl[i];

			dsi_phy_update_phy_timings(ctrl->phy, &display->config,

				is_cphy);

		}

	}



	/* back up existing rates to handle failure case */

	bkp_freq.byte_clk_rate = m_ctrl->ctrl->clk_freq.byte_clk_rate;

drivers/gpu/drm/msm/dsi-staging/dsi_panel.c

+8 −1
Original line number Diff line number Diff line
@@ -1334,7 +1334,7 @@ static int dsi_panel_parse_qsync_caps(struct dsi_panel *panel, 
static int dsi_panel_parse_dyn_clk_caps(struct dsi_panel *panel)

{

	int rc = 0;

	bool supported = false;

	bool supported = false, skip_phy_timing_update = false;

	struct dsi_dyn_clk_caps *dyn_clk_caps = &panel->dyn_clk_caps;

	struct dsi_parser_utils *utils = &panel->utils;

	const char *name = panel->name;
@@ -1368,6 +1368,13 @@ static int dsi_panel_parse_dyn_clk_caps(struct dsi_panel *panel) 
		return -EINVAL;

	}



	skip_phy_timing_update = utils->read_bool(utils->data,

				"qcom,dsi-dyn-clk-skip-timing-update");

	if (!skip_phy_timing_update)

		dyn_clk_caps->skip_phy_timing_update = false;

	else

		dyn_clk_caps->skip_phy_timing_update = true;



	dyn_clk_caps->dyn_clk_support = true;



	return 0;

drivers/gpu/drm/msm/dsi-staging/dsi_panel.h

+2 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -90,6 +90,7 @@ struct dsi_dyn_clk_caps { 
	bool dyn_clk_support;

	u32 *bit_clk_list;

	u32 bit_clk_list_len;

	bool skip_phy_timing_update;

};



struct dsi_pinctrl_info {