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Commit 8a8f7d20 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: add support of DP PHY bond mode for SA8195p"

parents 1ddeaa51 76823c35

arch/arm64/boot/dts/qcom/sa8195p-adp-star-display.dtsi

+52 −4
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ 
	};

};



&sde_dp {

&sde_dp0 {

	qcom,ext-disp = <&ext_disp>;

	qcom,dp-hpd-gpio = <&ioexp 8 0>;

	qcom,mst-fixed-topology-ports = <1 2>;
@@ -59,6 +59,42 @@ 
	};

};



&sde_dp1 {

	qcom,ext-disp = <&ext_disp>;

	qcom,dp-hpd-gpio = <&ioexp 9 0>;



	qcom,core-supply-entries {

		#address-cells = <1>;

		#size-cells = <0>;

		qcom,core-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "refgen";

			qcom,supply-min-voltage = <0>;

			qcom,supply-max-voltage = <0>;

			qcom,supply-enable-load = <0>;

			qcom,supply-disable-load = <0>;

		};

	};

};



&sde_edp {

	qcom,ext-disp = <&ext_disp>;

	qcom,dp-hpd-gpio = <&ioexp 11 0>;



	qcom,core-supply-entries {

		#address-cells = <1>;

		#size-cells = <0>;

		qcom,core-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "refgen";

			qcom,supply-min-voltage = <0>;

			qcom,supply-max-voltage = <0>;

			qcom,supply-enable-load = <0>;

			qcom,supply-disable-load = <0>;

		};

	};

};



&qupv3_se15_i2c {

	status = "ok";
@@ -82,7 +118,9 @@ 
			&dsi1_cdet_cfg_pins

			&dsi2_hpd_cfg_pins

			&dsi2_cdet_cfg_pins

			&dp_hpd_cfg_pins>;

			&dp0_hpd_cfg_pins

			&dp1_hpd_cfg_pins

			&edp_hpd_cfg_pins>;



		dsi1_hpd_cfg_pins: gpio0-cfg {

			pins = "gpio0";
@@ -104,10 +142,20 @@ 
			bias-pull-down;

		};



		dp_hpd_cfg_pins: gpio8-cfg {

		dp0_hpd_cfg_pins: gpio8-cfg {

			pins = "gpio8";

			bias-pull-down;

		};



		dp1_hpd_cfg_pins: gpio9-cfg {

			pins = "gpio9";

			bias-pull-down;

		};



		edp_hpd_cfg_pins: gpio11-cfg {

			pins = "gpio11";

			bias-pull-down;

		};

	};



	i2c-mux@77 {
@@ -415,7 +463,7 @@ 
				"none", "none";

	qcom,sde-mixer-display-pref = "primary", "none", "none",

				"none", "none", "none";

	connectors = <&dsi_dp1 &dsi_dp2 &sde_dp &sde_wb

	connectors = <&dsi_dp1 &dsi_dp2 &sde_dp0 &sde_dp1 &sde_edp &sde_wb

			&sde_sh0 &sde_sh1 &sde_sh2 &sde_shp

			&sde_card1 &sde_card2 &sde_card3>;

};

arch/arm64/boot/dts/qcom/sa8195p.dtsi

+11 −1
Original line number Diff line number Diff line
@@ -395,7 +395,17 @@ 
	vdda-1p2-supply = <&pm8195_1_l9>;

};



&sde_dp {

&sde_dp0 {

	vdda-1p2-supply = <&pm8195_1_l9>;

	vdda-0p9-supply = <&pm8195_3_l5>;

};



&sde_dp1 {

	vdda-1p2-supply = <&pm8195_1_l9>;

	vdda-0p9-supply = <&pm8195_3_l5>;

};



&sde_edp {

	vdda-1p2-supply = <&pm8195_1_l9>;

	vdda-0p9-supply = <&pm8195_3_l5>;

};

arch/arm64/boot/dts/qcom/sdmshrike-sde-pll.dtsi

+79 −5
Original line number Diff line number Diff line 
/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

/* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -65,9 +65,9 @@ 
		};

	};



	mdss_dp_pll: qcom,mdss_dp_pll@88ea000 {

	mdss_dp0_pll: qcom,mdss_dp_pll@88ea000 {

		compatible = "qcom,mdss_dp_pll_7nm";

		label = "MDSS DP PLL";

		label = "MDSS DP0 PLL";

		cell-index = <0>;

		#clock-cells = <1>;
@@ -75,9 +75,11 @@ 
		      <0x88eaa00 0x200>,

		      <0x88ea200 0x200>,

		      <0x88ea600 0x200>,

		      <0xaf03000 0x8>;

		      <0xaf03000 0x8>,

		      <0x88e8000 0x3c>,

		      <0x88e9000 0x1c0>;

		reg-names = "pll_base", "phy_base", "ln_tx0_base",

			"ln_tx1_base", "gdsc_base";

			"ln_tx1_base", "gdsc_base", "usb_dp_com", "usb_pll";



		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,
@@ -89,4 +91,76 @@ 
		clock-rate = <0>;

	};



	mdss_dp1_pll: qcom,mdss_dp_pll@88ef000 {

		compatible = "qcom,mdss_dp_pll_7nm";

		label = "MDSS DP1 PLL";

		cell-index = <1>;

		#clock-cells = <1>;



		reg = <0x88ef000 0x200>,

		      <0x88efa00 0x200>,

		      <0x88ef200 0x200>,

		      <0x88ef600 0x200>,

		      <0xaf03000 0x8>,

		      <0x88ed000 0x3c>,

		      <0x88ee000 0x1c0>;

		reg-names = "pll_base", "phy_base", "ln_tx0_base",

			"ln_tx1_base", "gdsc_base", "usb_dp_com", "usb_pll";



		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_DISP_AHB_CLK>,

			 <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>,

			 <&clock_gcc GCC_USB3_SEC_PHY_PIPE_CLK>;

		clock-names = "iface_clk", "ref_clk_src", "gcc_iface",

			"ref_clk", "pipe_clk";

		clock-rate = <0>;

	};



	mdss_dp2_pll: qcom,mdss_edp_pll@aec5000 {

		compatible = "qcom,mdss_edp_pll_7nm";

		label = "MDSS DP2 PLL";

		cell-index = <0>;

		#clock-cells = <1>;



		reg = <0xaec5000 0x200>,

		      <0xaec5a00 0x200>,

		      <0xaec5200 0x200>,

		      <0xaec5600 0x200>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "phy_base", "ln_tx0_base",

			"ln_tx1_base", "gdsc_base";



		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_DISP_AHB_CLK>,

			 <&clock_gcc GCC_PCIE_0_CLKREF_CLK>;

		clock-names = "iface_clk", "ref_clk_src", "gcc_iface",

			"ref_clk";

		clock-rate = <0>;

	};



	mdss_edp_pll: qcom,mdss_edp_pll@aec2000 {

		compatible = "qcom,mdss_edp_pll_7nm";

		label = "MDSS eDP PLL";

		cell-index = <1>;

		#clock-cells = <1>;



		reg = <0xaec2000 0x200>,

		      <0xaec2a00 0x200>,

		      <0xaec2200 0x200>,

		      <0xaec2600 0x200>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "phy_base", "ln_tx0_base",

			"ln_tx1_base", "gdsc_base";



		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_DISP_AHB_CLK>,

			 <&clock_gcc GCC_PCIE_0_CLKREF_CLK>;

		clock-names = "iface_clk", "ref_clk_src", "gcc_iface",

			"ref_clk";

		clock-rate = <0>;

	};



};

arch/arm64/boot/dts/qcom/sdmshrike-sde.dtsi

+225 −5
Original line number Diff line number Diff line
@@ -84,9 +84,9 @@ 
		qcom,sde-wb-clk-ctrl = <0x3b8 24>;



		qcom,sde-intf-off = <0x6b000 0x6b800

					0x6c000 0x6c800>;

					0x6c000 0x6c800 0x6d000 0x6d800>;

		qcom,sde-intf-size = <0x280>;

		qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";

		qcom,sde-intf-type = "dp", "dsi", "dsi", "dp", "dp", "dp";



		qcom,sde-pp-off = <0x71000 0x71800

					  0x72000 0x72800 0x73000 0x73800>;
@@ -611,9 +611,13 @@ 
		compatible = "qcom,dp-mst-sim";

	};



	sde_dp: qcom,dp_display@0{

	sde_dp0: qcom,dp_display@0{

		cell-index = <0>;

		compatible = "qcom,dp-display";

		qcom,intf-index = <0>;

		qcom,phy-index = <0>;



		qcom,bond-dual-ctrl = <1 0>;



		reg = <0xae90000 0x0dc>,

			<0xae90200 0x0c0>,
@@ -645,9 +649,9 @@ 
			 <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,

			 <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,

			 <&mdss_dp0_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,

			 <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,

			 <&mdss_dp0_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;

		clock-names = "core_aux_clk", "core_usb_ref_clk_src",
@@ -658,6 +662,7 @@ 
			"strm0_pixel_clk", "strm1_pixel_clk";



		qcom,phy-version = <0x420>;

		qcom,phy-mode = "dp";

		qcom,aux-cfg0-settings = [20 00];

		qcom,aux-cfg1-settings = [24 13];

		qcom,aux-cfg2-settings = [28 24];
@@ -673,6 +678,221 @@ 


		qcom,mst-enable;

		qcom,dp-aux-bridge-sim = <&sde_dp_mst_sim>;

		qcom,dsc-feature-enable;

		qcom,fec-feature-enable;

		qcom,widebus-enable;

		qcom,max-dp-dsc-blks = <2>;

		qcom,max-dp-dsc-input-width-pixs = <2048>;



		qcom,ctrl-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,ctrl-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-1p2";

				qcom,supply-min-voltage = <1200000>;

				qcom,supply-max-voltage = <1200000>;

				qcom,supply-enable-load = <21800>;

				qcom,supply-disable-load = <0>;

			};

		};



		qcom,phy-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,phy-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-0p9";

				qcom,supply-min-voltage = <880000>;

				qcom,supply-max-voltage = <880000>;

				qcom,supply-enable-load = <36000>;

				qcom,supply-disable-load = <0>;

			};

		};



		qcom,core-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,core-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "refgen";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};



	sde_dp1: qcom,dp_display@1{

		cell-index = <1>;

		compatible = "qcom,dp-display";

		qcom,intf-index = <2>;

		qcom,phy-index = <1>;



		reg = <0xae98000 0x0dc>,

			<0xae98200 0x0c0>,

			<0xae98400 0x508>,

			<0xae98a00 0x094>,

			<0x88efa00 0x200>,

			<0x88ef200 0x200>,

			<0x88ef600 0x200>,

			<0xaf02000 0x1a0>,

			<0x780000 0x621c>,

			<0x88ef040 0x10>,

			<0x88ed000 0x20>,

			<0xaee2000 0x034>,

			<0xae99000 0x094>;

		reg-names = "dp_ahb", "dp_aux", "dp_link",

			"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",

			"dp_mmss_cc", "qfprom_physical", "dp_pll",

			"usb3_dp_com", "hdcp_physical", "dp_p1";



		interrupt-parent = <&mdss_mdp>;

		interrupts = <13 0>;



		clocks =  <&clock_dispcc DISP_CC_MDSS_DP_AUX1_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>,

			 <&clock_gcc GCC_USB3_SEC_PHY_PIPE_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_LINK1_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO1_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>,

			 <&mdss_dp1_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,

			 <&mdss_dp1_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;

		clock-names = "core_aux_clk", "core_usb_ref_clk_src",

			"core_usb_ref_clk", "core_usb_pipe_clk",

			"link_clk", "link_iface_clk",

			"crypto_clk", "pixel_clk_rcg", "pixel_parent",

			"pixel1_clk_rcg", "pixel1_parent",

			"strm0_pixel_clk", "strm1_pixel_clk";



		qcom,phy-version = <0x420>;

		qcom,phy-mode = "dp";

		qcom,aux-cfg0-settings = [20 00];

		qcom,aux-cfg1-settings = [24 13];

		qcom,aux-cfg2-settings = [28 24];

		qcom,aux-cfg3-settings = [2c 00];

		qcom,aux-cfg4-settings = [30 0a];

		qcom,aux-cfg5-settings = [34 26];

		qcom,aux-cfg6-settings = [38 0a];

		qcom,aux-cfg7-settings = [3c 03];

		qcom,aux-cfg8-settings = [40 b7];

		qcom,aux-cfg9-settings = [44 03];



		qcom,max-pclk-frequency-khz = <675000>;



		qcom,dsc-feature-enable;

		qcom,fec-feature-enable;

		qcom,widebus-enable;

		qcom,max-dp-dsc-blks = <2>;

		qcom,max-dp-dsc-input-width-pixs = <2048>;



		qcom,ctrl-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,ctrl-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-1p2";

				qcom,supply-min-voltage = <1200000>;

				qcom,supply-max-voltage = <1200000>;

				qcom,supply-enable-load = <21800>;

				qcom,supply-disable-load = <0>;

			};

		};



		qcom,phy-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,phy-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-0p9";

				qcom,supply-min-voltage = <880000>;

				qcom,supply-max-voltage = <880000>;

				qcom,supply-enable-load = <36000>;

				qcom,supply-disable-load = <0>;

			};

		};



		qcom,core-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,core-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "refgen";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};



	sde_edp: qcom,dp_display@2{

		cell-index = <2>;

		compatible = "qcom,dp-display";

		qcom,intf-index = <3>;

		qcom,phy-index = <3>;



		reg = <0xae9a000 0x0dc>,

			<0xae9a200 0x0c0>,

			<0xae9a400 0x508>,

			<0xae9aa00 0x094>,

			<0xaec2a00 0x200>,

			<0xaec2200 0x200>,

			<0xaec2600 0x200>,

			<0xaf02000 0x2ac>,

			<0x780000 0x621c>,

			<0xaec2040 0x10>,

			<0x88e8000 0x20>,

			<0xaee1000 0x034>,

			<0xae9b000 0x094>;

		/* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */

		reg-names = "dp_ahb", "dp_aux", "dp_link",

			"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",

			"dp_mmss_cc", "qfprom_physical", "dp_pll",

			"usb3_dp_com", "hdcp_physical", "dp_p1";



		interrupt-parent = <&mdss_mdp>;

		interrupts = <14 0>;



		clocks =  <&clock_dispcc DISP_CC_MDSS_EDP_AUX_CLK>,

			 <&clock_gcc GCC_PCIE_0_CLKREF_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_EDP_LINK_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>,

			 <&mdss_edp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,

			 <&clock_dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;

		clock-names = "core_aux_clk", "core_ref_clk",

			"link_clk", "link_iface_clk",

			"pixel_clk_rcg", "pixel_parent",

			"strm0_pixel_clk";



		qcom,phy-version = <0x500>;

		qcom,phy-mode = "edp";

		qcom,aux-cfg0-settings = [24 00];

		qcom,aux-cfg1-settings = [28 13];

		qcom,aux-cfg2-settings = [2c 24];

		qcom,aux-cfg3-settings = [30 00];

		qcom,aux-cfg4-settings = [34 0a];

		qcom,aux-cfg5-settings = [38 26];

		qcom,aux-cfg6-settings = [3c 0a];

		qcom,aux-cfg7-settings = [40 03];

		qcom,aux-cfg8-settings = [44 37];

		qcom,aux-cfg9-settings = [48 03];



		qcom,max-pclk-frequency-khz = <675000>;



		qcom,dsc-feature-enable;

		qcom,fec-feature-enable;

		qcom,max-dp-dsc-blks = <2>;