Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 89e39f15 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: qcom: mdss: Fix switched bit clk rate after suspend-resume"

parents 589aab57 9a4af28a

drivers/clk/qcom/mdss/mdss-dsi-pll-14nm-util.c

+1 −1
Original line number Diff line number Diff line
@@ -1145,7 +1145,7 @@ void pll_vco_unprepare_14nm(struct clk_hw *hw) 
		return;

	}



	pll->vco_cached_rate = clk_hw_get_rate(hw);

	pll->vco_cached_rate = clk_get_rate(hw->clk);

	dsi_pll_disable(hw);

}

drivers/clk/qcom/mdss/mdss-dsi-pll-14nm.c

+4 −0
Original line number Diff line number Diff line
@@ -80,6 +80,7 @@ static struct dsi_pll_vco_clk dsi0pll_vco_clk = { 
			.name = "dsi0pll_vco_clk_14nm",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_ops_dsi_vco,

		},

};
@@ -92,6 +93,7 @@ static struct dsi_pll_vco_clk dsi0pll_shadow_vco_clk = { 
			.name = "dsi0pll_shadow_vco_clk_14nm",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_ops_shadow_dsi_vco,

		},

};
@@ -106,6 +108,7 @@ static struct dsi_pll_vco_clk dsi1pll_vco_clk = { 
			.name = "dsi1pll_vco_clk_14nm",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_ops_dsi_vco,

		},

};
@@ -120,6 +123,7 @@ static struct dsi_pll_vco_clk dsi1pll_shadow_vco_clk = { 
			.name = "dsi1pll_shadow_vco_clk_14nm",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_ops_shadow_dsi_vco,

		},

};

drivers/gpu/drm/msm/sde/sde_encoder.c

+7 −2
Original line number Diff line number Diff line
@@ -2674,6 +2674,7 @@ static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc, 
	struct sde_connector *sde_conn = NULL;

	struct sde_rm_hw_iter dsc_iter, pp_iter;

	struct sde_rm_hw_request request_hw;

	bool is_cmd_mode = false;

	int i = 0, ret;



	if (!drm_enc) {
@@ -2692,6 +2693,8 @@ static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc, 
	priv = drm_enc->dev->dev_private;

	sde_kms = to_sde_kms(priv->kms);

	connector_list = &sde_kms->dev->mode_config.connector_list;

	is_cmd_mode = sde_enc->disp_info.capabilities &

					MSM_DISPLAY_CAP_CMD_MODE;



	SDE_EVT32(DRMID(drm_enc));
@@ -2733,7 +2736,8 @@ static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc, 


	/* release resources before seamless mode change */

	if (msm_is_mode_seamless_dms(adj_mode) ||

			msm_is_mode_seamless_dyn_clk(adj_mode)) {

			(msm_is_mode_seamless_dyn_clk(adj_mode) &&

			 is_cmd_mode)) {

		/* restore resource state before releasing them */

		ret = sde_encoder_resource_control(drm_enc,

				SDE_ENC_RC_EVENT_PRE_MODESET);
@@ -2808,7 +2812,8 @@ static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc, 


	/* update resources after seamless mode change */

	if (msm_is_mode_seamless_dms(adj_mode) ||

			msm_is_mode_seamless_dyn_clk(adj_mode))

			(msm_is_mode_seamless_dyn_clk(adj_mode) &&

			is_cmd_mode))

		sde_encoder_resource_control(&sde_enc->base,

						SDE_ENC_RC_EVENT_POST_MODESET);

}